Electric grammars. Algorithmic design and construction of experimental music
circuits
Simone Pappalardo
Conservatorio Statale di Musica “O. Respighi” di Latina simpapp@yahoo.it
Andrea Valle
CIRMA-StudiUm - Universit`a di Torino andrea.valle@unito.it
ABSTRACT
The paper discusses a generative approach to the design of experimental electronic circuits for musical application. The model takes into account rewriting rules inspired by L-systems constrained by domain-specific features depend-ing on electronic components, and generates families of circuits. An integrated production pipeline is introduced, that ranges from algorithmic design to simulation up to hardware printing.
1. INTRODUCTION
A generative approach has been intensely pursued in the digital domain, i.e. where a certain generative system has an established connection between software and final out-put. Computer music has worked extensively on algorith-mic composition techniques that have been applied since its inception both to event organization and audio gener-ation [1]. On the other side, physical computing [2] has successfully tried in recent years to fill the gap between computation and the physical world, by linking algorith-mic design to a heterogeneous set of production systems, e.g. in the extensive applications of 3D printing. Concern-ing electronics, and in particular electronic circuit design, it can be observed that the latter is a complex task, as it involves accurate selection of components in relation to a specific desired output. Thus, algorithmic techniques are used on the design side mostly for circuit optimization. As an example, evolutionary algorithms have been used to de-sign circuits: the rationale is that in some cases a certain performance is expected and the algorithm is iteratively run so to design a circuit to fit the targeted performance [3]. In this sense, generation is constrained by an expected re-sult rather than focusing on the exploration of new behav-iors (see also [4] for AI techniques based on an evolution-ary computation for circuit design). Moreover, hardware layout for electronic components involves many critical steps, depending on both component features (packaging) and routing constraints (e.g. non overlapping of routes). Thus, a completely automated pipeline as required by a truly generative approach, linking algorithmic models to
Copyright: c 2017 Simone Pappalardo et al. This is
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final physical output (i.e. electronic components) is a dif-ficult task. On the other side, nowadays available tech-nologies seem promising in favoring such an approach, as a panoply of Electronic Design Automation (EDA) soft-ware solutions are available, that can be directly linked to automatic circuit printing. In the following, we discuss a generative methodology for audio circuit design, propose an application, and describe an integrated pipeline solution from circuit modeling to PCB printing.
2. ALGORITHMIC DESIGN FOR AUDIO CIRCUIT
Generative approaches to art and creativity are typically intended as ways to yield complex structures by defining compact formal procedures. A plethora of models and techniques has been defined in the last decades, includ-ing, among the others, formal grammars, fractals, cellular automata [5]. As such approaches are formal, they have been applied/mapped to various aesthetic domains, includ-ing e.g. visual art and music composition. The rationale at their base is to shift the focus from the final work to the meta-level, that of a system capable of generating various “legal”, “well-formed” outputs. In turn, outputs may be evaluated, e.g. filtered in terms of acceptance/refusal in re-lation to some (un)desired features, and the evaluation may be used to tune the system by means of a feedback loop. In short, algorithmic techniques like the aforementioned ones are mostly used to explore the output space of a system. In the domain of sound production, analog audio synthesis –far from being a dead end– has survived to digital audio and it is at the moment flourishing among musicians, in particular in hybrid systems that retain analog audio gen-eration while assigning control to digital modules. In the field of electronic circuits for music applications, modular systems that can be assembled in various ways are a stan-dard solution since the inception of analog electronic mu-sic, and recently various efforts have been made to create miniature, highly reconfigurable modular systems (e.g.
lit-tleBits1). However, as the assembly is left to the user, all
these systems are not suited for generative techniques. In this sense, the generative process should move to a lower hardware level. A generative approach to audio circuit de-sign has not been investigated, as far as we know, as typi-cal audio circuits implement well-defined schemes that are a priori constrained in relation to specific needs, e.g. noise reduction optimization or adherence to a certain already
tablished model, as in the case of guitar pedal effects. On the other side, many experimental music practices focus on the manipulation of analog audio circuits with a clear exploratory aim [6]. As an extreme example, the popular practice of circuit bending [7] even proposes a paradoxi-cal “anti-theory” as a knowledge background for a totally empirical approach to electronic hacking. Differently from the previous empirical approaches but sharing the same ex-ploratory perspective, we propose a generative approach to audio circuit design for experimental music. The main aim of our project is to produce families of circuits, sharing some basic features, that can be printed automatically, so that each board is unique while retaining a family resem-blance with the other from the same generative model. The design methodology is a three-step process:
1. Model retrieval: as a first step, an already estab-lished audio circuit is taken into account, so to start with a well-know and working example;
2. Functional decomposition: the circuit is theoreti-cally decomposed into functional units that can be thought as closed elements provided with inputs and outputs. These units can include various electronic component configurations. Granularity at the single component level (e.g. diode) is too basic to provide an operative base for generation, as too many con-straints would have to be taken into account.
3. Rule-based re-organisation: functional units are con-sidered as symbols to be arranged in strings follow-ing a specific formalization.
While conceptually separated, the three steps are tightly in-tegrated, as there is a constant feedback loop among search-ing for suitable audio circuits, investigatsearch-ing about their fit-ting into a modular approach, and assessing the robust-ness in scaling up component assembly via generative pro-cedure. In the following, we will discuss the previous methodology in relation to a case study.
3. MODEL RETRIEVAL AND FUNCTIONAL DECOMPOSITION IN A TEST CASE In this section we discuss audio analog electronics, that is, in reference to the previous process, both models (1) and decomposition (2). We will discuss a specific test case to show various emerging issues, but the former is meant as an example of the previously introduced, general method-ology. As already said, while it might be desirable to un-couple electronic circuit design from generative modeling, there is a feedback loop between the domain to be genera-tively modeled (electronic circuits) and the modeling sys-tem (see later). In general terms, our basic design choice was targeted to define an expansion procedure of a certain basic circuit. Indeed, other circuit designs may be taken into account as candidates.
Our aim has been to look for an already established audio schematic (methodology, step 1) provided with two fea-tures. First, it should be expandable by iterating a limited set of basic units, as the goal of the main electronic circuit
Figure 1. Diode clipping circuit.
Figure 2. Diode clamping circuit.
is to link some independent object characterized by audio input and output (methodology, step 2). Second, it should provide a spectral enrichment (a music desideratum) with-out a final amplitude overload (an audio constraint related to generative procedure, as iteration results in stacking an undefined number of components).
In relation to step 1, it can be observed that diodes ap-plications have been widely used in audio. in particular, diode clipping (Figure 1) is often used in analog and audio circuits to create distortion effects or to protect a device’s input from possible current overloads: as a consequence, various schematics implementing this technique are avail-able (e.g. [8]). Diodes used in analog effects for guitar generally clip when the input signal voltage reaches the forward threshold voltage of the component. For our cir-cuit we decided to work with Schottky diodes so to have a very low clipping threshold (typically 0.2 V against 0.7 V of a silicon type).
In classical analog distortion guitar effects, the amplitude of the input signal is limited in either directions by a fixed amount. Indeed, in these devices, the reference threshold voltage for diodes is the circuit ground, so that the input signal clips at the small forward voltage of the forward bi-ased diode. In practical applications, the threshold voltage of the diode, and thus therefore the signal clipping point, can be set to any desired value by increasing or decreas-ing the reference voltage [9]. It is therefore theoretically possible to modulate the clipping threshold of a wave by setting an audio-controlled variable threshold as the for-ward biasing of the diode. In our case, the threshold of the diode is controlled by a clamping circuit [10] (Figure 2). In order both to isolate the effects of two circuits (clamping and clipping) and to control impedances to implement a simulation of an audio-modulated diode with Spice3 [11], we improved the theoretical schematics in Figures 1 and 2 by introducing two operational amplifiers, to be used as voltage followers. The resulting circuit is shown schemat-ically in Figure 3. It is still a theoretical circuit but suffi-cient to obtain a simulation of a “carrier” sine wave (220 Hz) dynamically clipped by another sinusoidal “modula-tor ” (439 Hz). Figure 4 shows a new simulation of the
out
Figure 3. Half wave diode-modulated clipping (dmc)
0ms
30ms
60ms
90ms
V
4
.
2
-V
2
.
0
-V
0
.
2
V(out)
Figure 4. Half wave dmc with C = 220 Hz and M = 1239 Hz.
same schematic, this time featuring a 220 Hz carrier and 1239 Hz modulator. This schematic allows the modulation of the negative half-waves of a carrier sine by changing at audio rate the voltage reference at the anode of a diode. In order to modulate both negative and positive parts of the carrier sine wave, Figure 5 shows the implementation of a duplication/reversal of the clamping schematic. Such a clamping circuit is intended to limit a third modulating wave in the positive range. This signal is used to induce a fluctuation in the voltage at cathode of a further diode that modulates the positive part of the carrier half-wave.
Figure 5 shows a Spice3 simulation with positive modula-tor = 1123 Hz, negative modulamodula-tor = 439 Hz, and carrier = 220 Hz.
The outlined schematic can be expanded by a systematic development, through a nesting and multiplication of mod-ulating objects around the axis of the carrier signal, thus fulfilling the requirement of step 2 of our methodology, that prepares rule-base organization (step 3). In order to al-low the nesting of elements, we took advantage of typical features of operational amplifiers. These components (op amps, as commonly referred), thanks to their impedance features and their ease of use, allow to simply cascade sev-eral parts, adding the possibility of frequency control by
0ms 40ms 80ms 120ms V 4 . 2 -V 0 . 0 V 4 . 2 V(out) C1 0.1µf 1N5817 D1 V2 SINE(0 2 439) V1 SINE(0 2 220) U1 D2 1N5817 V3 9 V4 9 U2 R1 1Meg C2 0.1µf 1N5817 D3 V5 SINE(0 2 1123) U3 D4 1N5817 V+ -V V+ -V V+ -V out V+ -V .TRAN 500ms Carrier Modulator -Modulator +
Figure 5. A modified version for full wave modulation dmc.
Figure 6. a) dc+.
means of inserting few capacitors. In our schematic model we add both a voltage follower object to use for coupling the various circuit each other, and an op amp input am-plifier to filter, amplify and/or attenuate three input sig-nals: carrier, negative modulator, positive modulator. The schematic model can be, then, decomposed into five units (see later): dc+, dc-, buffer, sig in, sig out.
Figures 6 to 10 show all the schematics of the final single objects. Figure 11 shows the complete root circuit ready for a Spice simulation. Colored blocks represent previ-ously discussed components, that is, a → dc+; b → dc-; c → buffer; d →sig in; e → sig out (for other letters, see Section 4, and the companion Figure 13). Figure 12 shows a physical test implementation of the “root” circuit, a min-imal assemblage of the components that acts as starting state for generation.
4. RULE-BASED RE-ORGANIZATION In general terms, many formalisms are available as gen-erative models to govern an arrangement of audio compo-nents. In our case, we have explored systems [12].
L-Figure 7. b) dc-.
Figure 8. c) buffer.
systems have been proposed in biology as formal models to describe natural shapes that exhibit a clear generative behavior, i.e. an accumulation of features resulting from a growing pattern. They have originally proven successful in modeling plants, and then inspired algorithmic approaches to biological morphologies (shells, sponges, seaweed) [13] [14]. As formal systems, and apart from their interpreta-tion in the biological domain, they have been widely used in generative art, including algorithmic music composi-tion. In relation to our case, the choice of L-systems has been driven by considering an electric circuit, if not a tree, at least as a sort of vegetable rhizome. Hence the idea of recursively expanding a basic topology into a more com-plex network. Analogously to what happened in the model retrieval step, other formalisms may be explored.
L-systems are formal grammars in which a set of paral-lel rewriting rules (“production rules”) is applied against an initial sequence of symbols (the “axiom”). Production rules allow to generate new sequences of symbols against which the former can be applied again. Even if the result-ing morphology depends on the interpretation of symbols in a certain domain, the formal system structurally encodes features of a recursive organization. The following model for audio analog electronic circuit is inspired by L-systems. It can be defined as
E = (V, ω, P ) where
V = {a, b, c, d, e} is the set of symbols,
ω = d ∗ @1 d ∗ @2 d ∗ @3 c1@4 a2@4 b3@4 c4@5 e5@∗
Figure 9. d) sig in.
Figure 10. e) sig out.
is the axiom, and P :
a → c3@(k + 1) b2@(k + 1) c(k + 1)@(k + 2) a(k + 2)@4 b → c2@(k + 3) a3@(k + 3) c(k + 3)@(k + 4) b(k + 4)@4 is the production ruleset.
As a variation on standard L-systems, the proposed model includes integers associated to each symbol in the form i@o, where @ is a syntactic separator. The symbol k repre-sents an integer associated to the complete rewriting n (i.e. application of all rules), so that k = n × 4. Empty spaces and brackets have only a typographical meaning for sake of readability. In the interpretation context, only the string resulting from the last rewriting is taken into account. Each symbol from V is associated to the relative electric compo-nent (see Section 3). The symbols i and o are interpreted as labels respectively for input and output ports. Thus, a sym-bol like b2@14 indicates that the component b has an input port labeled 2 and an output port labeled 14. The symbol ∗ represents a null value: it can be seen that components d have a null input, as they are signal generators that feed the circuit, while e has a null output, being itself the output of the system. In order to define the topology of the circuit, port labels are taken into account, and input ports are con-nected to output ones with the same label, the signal flow-ing from output to input. Graphical interpretation of the strings allows to inspect visually the resulting electronic topologies. The following graphs have been obtained by automatically scripting the dot language for graph
visual-U1 V1 9 9 V2 C1 330nF R2 100k R4 949meg R5 51k 100k R1 V4 SINE(0 1 405) U2 R3 267k R6 47kR7 33k C3 20pF C4 330nF C5 10µF D1 1N5817 V5 SINE(0 1 440) U3 R8 267k R9 47k R10 33k C2 20pF C6 330nF C7 10µF U4 C8 330nF R11 100k R12 949meg R13 51k 100k R14 V3 SINE(0 1 440) U5 R15 267k R16 47k R17 33k C920pF C10 330nF C11 10µF D2 1N5817 C12 330nF R18 47k U6 R19 50k R20 50k C13 2.2µF C14 330nF R21 47k U7 V+ V+ -V -V out V-V+ -V V+ -V V+ -V V+ V+ -V V+ -V V+ -V .TRAN 500ms d*@3 d*@1 d*@2 b3@4 a2@4 c1@4 c4@5 e5@*
Figure 11. Root circuit (axiom).
Figure 12. Root circuit, first test.
ization [15]. Figure 13 shows the topology of the circuit of Figure 11 in relation to its modeled decomposition into the axiom ω. Each component is colored in relation to its type, and labeled according to the mapped symbol, like in Figure 11. It can be seen that output ports are connected to input ports with the same identifier. Figure 14 shows the first application of the ruleset (n = 1).
The definition of the formal system has been driven by se-mantic constraints, i.e. by taking into account viable elec-tronic connections. While increasing n, the resulting string shows some spurious artifacts, in terms of its electronic in-terpretation. Figure 15 shows the topological graph with n = 2 (labels have been replaced with the component types). It is apparent from Figure 15 that buffers at the graph’ side are misplaced in the electronic interpretation, as they are isolated. To solve this issue, a recursive pruning strategy is applied to the graph, so that no isolated buffers are present in the final graph. Figure 16 shows the graph of Figure 15 after pruning.
5. AN INTEGRATED PIPELINE
While algorithmic modeling of electronic circuit topolo-gies can have a theoretical interest, it is indeed very far from a practical application. The aim of a generative ap-proach is indeed to obtain circuits whose complexity can-not be reached by hand design and that are (o should be) still guaranteed to work by the system definition itself. This requires an integrated automatic pipeline, ideally from for-mal model seamlessly to PCB printing. The implemented solution is shown in Figure 18. Grey boxes represent used
b3@4 c4@5 d*@1 c1@4 e5@* d*@3 a2@4 d*@2
Figure 13. Axiom, with connection labels.
a7@4 c4@5 c2@8 c8@9 c3@6 c6@7 e5@* d*@2 b2@6 a3@8 d*@1 c1@4 d*@3 b9@4
Figure 14. First rewriting, with connection labels.
softwares, while white boxes are internal blocks developed to perform specific functions. Plain text labels represent textual data. The generative model has been implemented in SuperCollider [16], an audio-targeted programming lan-guage that features high-level data collection manipula-tion. The SuperCollider component performs two task: generation and mapping. L-Generator is the module im-plementing the L-system generation: it takes an L-system specification as a textual input, and output a string (as a result of rewriting). The string is fed into the Parser that converts it into a data structure apt to be further manipu-lated by the Pruner module. The resulting data structure can then be mapped into other formats. The mapping task can be seen as a software gluing process. The DotGener-ator creates a dot file to be subsequently rendered by the dot program as a visual file. As discussed, this is instru-mental in rapidly understanding the behavior of the gener-ation process. LTGenerator creates input files (in the “asc” ASCII format) for the LTSpice IV software [17]. LTSpice IV includes simulation of the circuit via Spice3 (includ-ing audio generation, a crucial features in our case) and schematic drawing. In order to generate asc files, compo-nent descriptions are stored in specification templates (spec file), in which opportune textual replacements for identi-fiers and positions are performed. Component circuits (a– e) are algorithmically placed on the board by following a simple carriage return strategy over a fixed width grid and using textual labeling of input and output as internal
ref-buffer buffer buffer dc+ dc+ dc+ buffer buffer dc-buffer out dc-buffer buffer buffer buffer dc-sigIn buffer dc+ buffer sigIn buffer buffer sigIn
Figure 15. Second rewriting.
out buffer buffer buffer buffer dc+ dc+ buffer dc- dc-buffer buffer buffer dc-sigIn buffer dc- dc+ sigIn buffer sigIn dc+
Figure 16. Second rewriting, pruned.
erences. Figure 23 shows the circuit of Figure 17, as con-verted by LTGenerator into asc format and drawn by LT-Spice VI, with a zoomed component for sake of readability. Figures 20 and 19 show sonograms and waveforms from Spice 3 audio simulation of a very large circuit, obtained by four rewritings. It can be seen that complex spectra are easily obtained, with many partials in various harmonic re-lations. Spectra are sensitive to small parameter variations, thus ensuring a varied palette that can be exported as a user control (e.g. in the case of the three modulating frequen-cies, the latter can be associated to rotary controls on the final board). While Figure 19 illustrates a fixed spectrum, Figure 20 shows an evolving one, resulting from real-time parameter tweaking. While these results from extensive tests –matching the typical flavor of analog audio modu-lation but in a very rich way– are very encouraging, the main (in fact, surprising) drawback of simulation is that it has proved to be far from accurate (see later), so a real test phase has to be performed on the final hardware cir-cuits. The asc format is also used as an interchange format
to communicate with EasyEDA2, a web-based EDA tool
suite. EasyEDA has functionalities to facilitate (even if not to fully automate) routing for printed circuit board layouts and to directly manufacture printed circuit boards. In this way, it is possible to link the formally generated
specifica-2https://easyeda.com/
tion file to PCB printing. Figure 22 shows the root circuit PCB (i.e. the axiom) obtained by running the autorouting procedure in EasyEDA.
6. OPEN ISSUES
At the moment of writing, we have tested physical circuits on breadboard, generated layout diagrams, run extensive simulations, while we have still not printed PCBs. Thus, we cannot evaluate the very final product of the pipeline. In any case, two main issues have emerged.
Simulation vs. Reality. For each object, various tests were made in order to find the best configuration in terms of matching between Spice3 simulation results and real physical behavior (tested on breadboard implementations). This is a crucial point, as –in order to simulate with a good approximation the circuit even after several expansions by the generative system– it is essential that the Spice simula-tion is very close to the actual behavior of the circuit. Oth-erwise, unpredictable, non-functional results may emerge in the printed circuit. As a matter of facts, real circuits as-sembled on breadboard have always shown relevant differ-ences in their behavior if compared to Spice3 simulations. Three main factors account for these differences:
– the power supply quality which must be opportunely and recursively filtered, unlike in the simulated schematic; – the extensive need, between input and output of several op amp, for decoupling capacitors, not necessary (at least in the same amount) in the simulated circuit;
– the placement of the components on the board, that may create ground loops, again absent from Spice.
The physical circuit is usually more sensitive to small, some-times timy, variations in the starting conditions. Here, non-linearity of the components seems to be more visible. For example, in our case, small variations in the signal ampli-tudes (modulating and/or carrier) result in large differences in the resulting output. The simulation in Spice seems to smooth out the nonlinearity of the components. In this sense, the diode clamping (circuits a-dc+ and b-dc-) is the most sensitive to small variations of the input signals. We tried physically different circuits to limit and optimize the results. in order to allow a more flexible modulation of the threshold of the diode we chose to use a circuit that allows us to select by means of a potentiometer the amount of dc-offset output. A different amounts of dc-offset corresponds to a greater or lesser depth of action of the modulating diode. Pipelining. Figure 21 shows an ideal, 5-step model. First, an abstract topology of the circuit, such as the ones in Fig-ure 14-16, is generated (1). Then, the topology is mapped onto an actual electronic topology, incorporating data from real electronic components, but without any metrics re-ferred to the final circuit layout, so that a simulation can be rendered (2). The electronic circuit should be rendered as a schematic in order to provide a standard visual feedback on the result (3). Finally, the circuit schematic should be con-verted into a description of the physical layout, including component packaging and routes (4), so to be delivered for PCB printing (5). Candidates for step 1 include substan-tially all available programming languages, better if shifted towards high-level due to data manipulation in the formal
dc+
op amp op amp op amp op amp op amp
dc+ dc+ dc+ dc+
dc-op amp op amp op amp
out sigIn op amp dc-op amp dc+ dc- dc- dc-op amp dc+ sigIn dc-op amp op amp op amp op amp dc-
dc-dc+ op amp op amp op amp
sigIn
Figure 17. Third rewriting, pruned.
SW HW
L-Generator string
Parser data structure Pruner data structure
DotGenerator dot file LtGenerator asc file LtSpice audio file EasyEDA Dot graphic file l-system spec file graphic file graphic file Generation Mapping SuperCollider PCB
Figure 18. Implemented integrated pipeline.
Time (s) 0 0.5 0 2·104 F re qu en cy (H z) 0.25 Time (s) 0 0.5 -0.577 0.5909 0 Time (s) 0 0.5 0 2·104 F re qu en cy (H z) 0.25 Time (s) 0 0.5 -0.577 0.5909 0
Figure 19. LTSpice audio simulation with 4 rewritings, 55, 44, 3345.7 Hz.
model. A standard candidate for step 2 is indeed Spice3, that takes as its input a so-called netlist, i.e. a textual spec-ification of components and connections, and is able to run simulation (including audio) and perform various analysis. Various software packages are available for steps 4 and 5, like e.g Autodesk Eagle. Actual available softwares for electronic layout are intended as computer-aided software for interactive editing toward the final layout organization, not as automated tools. A critical issue in relation to the ideal pipeline is that all the data should automatically tran-sit from one step to the other. As an example, our choice (EasyEDA) has been determined by file format compatibil-ity with LTSpice IV. On one side, schematic capture
soft-Time (s) 0 1 0 2·104 F re qu en cy (H z) 0.5 Time (s) 0 1 -0.6162 0.6022 0 Time (s) 0 1 0 2·104 F re qu en cy (H z) 0.5 Time (s) 0 1 -0.6162 0.6022 0
Figure 20. LTSpice audio simulation with 4 rewritings, 439, 440, 442.5 Hz.
Generative design Electronic modelling Circuit visualisation Layout organisation PCB printing
1 2 3 4 5
Figure 21. Ideal pipeline.
wares (as required by 4) are intended for design, and in-cludes Spice3 as a simulation engine, so that typically they are able to export netlist files but not to import them. This depends on the fact that such a passage would require au-tomatic layout for drawing circuit schematic. In our case, we solved by defining a grid algorithm. On a different but correlated side, EDA softwares (5) aim at computer-aided layout design, but not at a fully automatic one. Autorout-ing facilities are available, but, as final physical layout de-pends on such a large number of parameters, automation is only partially possibles. Of course, very large, auto-matically generated circuits still require a large amount of hand-operated fine tuning of the layout before printing.
7. CONCLUSIONS
While still at a prototypical stage, we believe that our ap-proach has shown potential interest for experimental computer-design of audio analog synthesis, as can be seen from re-sulting signals in Figure 20 and 19. Generative models allow to describe not circuits, but families of circuits, that share some features but may differ one from each other by details. Thus, with automatic PCB routing, it could be
pos-Figure 22. PCB for root circuit via autorouting.
sible to create singleton, unique synthesizers/processors. Indeed, the most delicate point is the layout for PCB print-ing of large generated circuits, that is still not robust from an automation perspective. But, once fine-tuned in relation to real physical behavior, circuits can be simulated, and only the final step (5) requires handcrafted operations. As a future work, we are planning to print PCB boards and test real final complex circuits, to analyze other analog cir-cuits in order to decompose them, so that other generative models may be taken into account.
U0 C1 330nFR2 100k R3 949meg R4 51k 100kR5 D6 1N5817 C7 330nFR8 47k U9 U10 C11 330nFR12 100k R13 949meg R14 51k 100kR15 D16 1N5817 U17 C18 330nFR19 100k R20 949meg R21 51k 100kR22 D23 1N5817 C24 330nFR25 47k U26 C27 330nF R28 47k U29 C30 330nFR31 47k U32 U33 R34 33k R35 267k R36 47k C37 20pF C38 330nF C39 10µF C40 330nF R41 47k U42 C43 330nF R44 47k U45 U46 C47 330nFR48 100k R49 949meg R50 51k 100kR51 D52 1N5817 C53 330nF R54 47k U55 U56 C57 330nFR58 100k R59 949meg R60 51k 100kR61 D62 1N5817 U63 C64 330nFR65 100k R66 949meg R67 51k 100kR68 D69 1N5817 C70 330nF R71 47k U72 U73 C74 330nFR75 100k R76 949meg R77 51k 100kR78 D79 1N5817 U80 C81 330nFR82 100k R83 949meg R84 51k 100kR85 D86 1N5817 C87 330nF R88 47k U89 C90 330nFR91 47k U92 C93 330nFR94 47k U95 U96 R97 33k R98 267k R99 47k C100 20pF C101 330nF C102 10µF C103 330nF R104 47k U105 U106 C107 330nFR108 100k R109 949meg R110 51k 100kR111 D112 1N5817 C113 330nF R114 47k U115 U116 C117 330nFR118 100k R119 949meg R120 51k 100kR121 D122 1N5817 C123 330nFR124 47k U125 C126 330nF R127 47k U128 U129 C130 330nFR131 100k R132 949meg R133 51k 100kR134 D135 1N5817 C136 330nFR137 47k U138 U139 C140 330nFR141 100k R142 949meg R143 51k 100kR144 D145 1N5817 C146 330nFR147 47k U148 R149 50k R150 50k C151 2.2µF U152 R153 33k R154 267k R155 47k C156 20pF C157 330nF C158 10µF U159 C160 330nFR161 100k R162 949meg R163 51k 100kR164 D165 1N5817 U166 C167 330nFR168 100k R169 949meg R170 51k 100kR171 D172 1N5817 C173 330nF R174 47k U175 U176 C177 330nFR178 100k R179 949meg R180 51k 100kR181 D182 1N5817 U183 C184 330nFR185 100k R186 949meg R187 51k 100kR188 D189 1N5817 V1 V V2 V V+ -V V+ 15 4 V+ -V 2 16 V+ -V V+ 3 16 V+ -V V+ 15 4 V+ -V 3 14 V+ -V 16 17 V+ -V 3 14 v+ -v * 2 V+ -V 16 17 V+ -V 14 15 V+ -V V+ 3 16 V+ -V 14 15 V+ -V V+ 15 4 V+ -V V-2 14 V+ -V 3 14 V+ -V V-17 4 V+ -V V+ 15 4 V+ -V 4 5 V+ -V 14 15 V+ -V 16 17 v+ -v * 1 V+ -V 2 16 V+ -V V-2 14 V+ -V 1 4 V+ -V V-2 14 V+ -V 14 15 V+ -V 3 14 V+ -V V-17 4 V+ -V 16 17 V+ -V V+ 3 16 V+ -V 2 16 * 5 v+ -v * 3 V+ -V V-17 4 V+ -V V-2 14 V+ -V 2 16 V+ -V V-17 4 V+ -V V+ 3 16 v+ -v U0 C1 330nF R2 100k R3 949meg R4 51k 100k R5 D6 1N5817 C7 330nF R8 47k U9 U10 C11 330nF R12 100k R13 949meg R14 51k 100k R15 D16 1N5817 U17 C18 330nF R19 100k R20 949meg R21 51k 100k R22 D23 1N5817 C24 330nF R25 47k U26 C27 330nF R28 47k U29 C30 330nF R31 47k U32 U33 R34 33k R35 267k R36 47k C37 20pF C38 330nF C39 10µF C40 330nF R41 47k U42 C43 330nF R44 47k U45 U46 C47 330nF R48 100k R49 949meg R50 51k 100k R51 D52 1N5817 C53 330nF R54 47k U55 U56 C57 330nF R58 100k R59 949meg R60 51k 100k R61 D62 1N5817 U63 C64 330nF R65 100k R66 949meg R67 51k 100k R68 D69 1N5817 C70 330nF R71 47k U72 U73 C74 330nF R75 100k R76 949meg R77 51k 100k R78 D79 1N5817 U80 C81 330nF R82 100k R83 949meg R84 51k 100k R85 D86 1N5817 C87 330nF R88 47k U89 C90 330nF R91 47k U92 C93 330nF R94 47k U95 U96 R97 33k R98 267k R99 47k C100 20pF C101 330nF C102 10µF C103 330nF R104 47k U105 U106 C107 330nF R108 100k R109 949meg R110 51k 100k R111 D112 1N5817 C113 330nF R114 47k U115 U116 C117 330nF R118 100k R119 949meg R120 51k 100k R121 D122 1N5817 C123 330nF R124 47k U125 C126 330nF R127 47k U128 U129 C130 330nF R131 100k R132 949meg R133 51k 100k R134 D135 1N5817 C136 330nF R137 47k U138 U139 C140 330nF R141 100k R142 949meg R143 51k 100k R144 D145 1N5817 C146 330nF R147 47k U148 R149 50k R150 50k C151 2.2µF U152 R153 33k R154 267k R155 47k C156 20pF C157 330nF C158 10µF U159 C160 330nF R161 100k R162 949meg R163 51k 100k R164 D165 1N5817 U166 C167 330nF R168 100k R169 949meg R170 51k 100k R171 D172 1N5817 C173 330nF R174 47k U175 U176 C177 330nF R178 100k R179 R180 100k R181 D182 1N5817 U183 C184100k R188 D189 V1 V V2 V V+ -V V+ 15 4 V+ -V 2 16 V+ -V V+ 3 16 V+ -V V+ 15 4 V+ -V 3 14 V+ -V 16 17 V+ -V 3 14 v+ -v * 2 V+ -V 16 17 V+ -V 14 15 V+ -V V+ 3 16 V+ -V 14 15 V+ -V V+ 15 4 V+ -V V-2 14 V+ -V 3 14 V+ -V V-17 4 V+ -V V+ 15 4 V+ -V 4 5 V+ -V 14 15 V+ -V 16 17 v+ -v * 1 V+ -V 2 16 V+ -V V-2 14 V+ -V 1 4 V+ -V V-2 14 V+ -V 14 15 V+ -V 3 14 V+ -V V-17 4 V+ -V 16 17 V+ -V V+ 3 16 V+ -V 2 16 * 5 v+ -v * 3 V+ -V V-17 4 V+ -V V-2 14 V+ -V 2 16 V+ -V V-17 4 V+ 3 16 v+ -v
Figure 23. LTSpice drawing from automatic generated asc file, third rewriting, with a zoomed module.
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