Conclusions
Since their rediscovery in 1995, Low-Density Parity-Check (LDPC) codes have gained the momentum of the international scientific community due to their unequal error correction capability. In fact, Chung et al. were able to measure Bit Error Rate (BER) performance as close as 0.0045 dB from the Shannon limit [Chung et al., 2001]. Therefore LDPC codes are today the preferred choice for next-generation communication standards such as WLAN , DVB-S2, WiMax.
The aim of this thesis work has been the FPGA prototyping of a multi-rate LDPC codes decoder compliant with the forthcoming IEEE 802.11n high-throughput extension for Wi-Fi applications. The decoder Intellectual Property (IP) macrocell has been developed at the University of Pisa in the framework of a research project in collaboration with STMicroelectronics. The FPGA prototyping is considered as a necessary step toward the silicon implementation on the STMicroelectronics CMOS 65 nm standard cells technology.
The prototyping environment consists of a Nallatech PCI-BenNUEY motherboard equipped with Xilinx FPGAs and off-chip Zero Bus Turnaround (ZBT) SRAM. The prototyping board is connected to a host PC via PCI bus, thus acting as a dedicated hardware accelerator.
The prototype has been fitted on a Xilinx 8Mgates Virtex-II FPGA. Off-chip and on-chip memory resources have been used to implement the communication between the host PC and the prototype. The PCI communication subsystem (called application interface) runs at 40 MHz as required by the PCI physical interface already integrated on-board [NAL, 2004]. For the LDPC codes decoder the clock frequency is 90 MHz, which is the maximum achievable frequency after the place&route design phase. The estimated clock frequency for the ASIC implementation on CMOS 65nm is 240 MHz. The achieved device occupation for the whole prototype system is 13.82 % CLBs, where 12.73 % CLBs is for the LDPC codes decoder design unit and 1.09 % CLBs for the application interface design unit.
The PCI communication subsystem has been described with a highly parametrical VHDL code to enable the reuse of this work for prototyping a generic IP macrocell. In this respect, it is worth noting the small area overhead (only 7.87 % of the whole prototype system) introduced by this design unit. The subsystem can perform both size and frequency conversion. The former enable the selection of any aspect ratio for the on-chip and off-chip buffers, while the latter decouples the frequency of the PCI communication subsystem (fixed at 40 MHz) from the frequency of the implemented IP macrocell.
About the limits of this work, it has been highlighted that the LDPC codes decoder prototype is configured only for the short codeword (648 bits), i.e. the multi-length configurability is not supported. Furthermore, the multi-rate configurability is implemented, but it can be managed only at compile time, i.e. when programming the device.
As future improvements, the PCI interface could be used to configure the decoder at run- time. This comes at no extra costs and requires modification mainly at software level. Concerning the multi-length support, a decoder covering all codeword lengths is build up by parallelizing the 648-bits decoder implemented in this thesis work, thus affecting only device occupation. The expected device occupation for the full decoder is about 52% of the Xilinx 8Mgates Virtex-II FPGA.
