1. SPACEWIRE STATE OF THE ART STUDY... 4

I

INTRODUCTION ... 1

1. SPACEWIRE STATE OF THE ART STUDY... 4

1.1 The ECSS System... 4

1.2 The SpaceWire Standard... 5

1.2.1 Physical level ... 6

1.2.1.1 Cables... 6

1.2.1.2 Connectors... 7

1.2.1.3 Cable assembly... 8

1.2.1.4 PCB and backplane tracking ... 8

1.2.2 Signal level... 9

1.2.2.1 Signal level and noise margin... 9

1.2.2.2 Data encoding... 11

1.2.3 Data signalling rate ... 12

1.2.4 Character level ... 12

1.2.4.1 Data characters ... 13

1.2.4.2 Control characters and control codes... 13

1.2.4.3 Parity for error detection ... 14

1.2.4.4 Transmit bit pattern on link start ... 15

1.2.4.5 Time code and time interface ... 15

1.2.5 Exchange level ... 16

1.2.5.1 Initialization ... 16

1.2.5.2 Flow control ... 17

1.2.5.3 Detection of disconnect errors... 17

1.2.5.4 Detection of parity errors... 17

1.2.5.5 Link error recovery... 17

1.2.6 Packet level ... 18

1.2.7 Network level... 19

1.2.7.1 Wormhole routing ... 20

1.2.7.2 Header deletion... 21

1.2.7.3 Virtual channels... 23

1.2.7.4 Path addressing... 23

1.2.7.5 Logical addressing... 24

1.2.7.6 Regional addressing ... 25

1.2.7.7 Group adaptive routing... 26

1.2.7.8 Configuration space... 27

Contents

II

1.3 Protocol Identification ... 28

1.4 Remote Memory Access Protocol... 29

1.5 Current SpW IP cores available into the market ... 31

1.5.1 Aeroflex Gaisler... 31

1.5.2 STAR-Dundee... 33

1.5.3 NASA Goddard... 35

1.5.4 SpaceWire UK ... 36

1.5.5 CESR - CNRS... 37

2. IP DATABASE AND PROJECT ENVIRONMENT ... 39

2.1 IP database directory structure ... 39

2.1.1 Source directory ... 40

2.1.2 Simulation directory... 40

2.1.3 Synthesis and implementation directory ... 40

2.2 The SpaceWire router IP... 41

2.2.1 SpW Router Core ... 41

2.2.2 SpW Interface ... 42

2.2.3 AMBA AHB wrapper and RMAP decoder... 43

2.3 Design and development environment... 44

2.3.1 Step one: Design creation... 45

2.3.2 Step two: Design verification – Pre-Synthesis simulation ... 45

2.3.3 Step three: Design Synthesis/EDIF generation ... 45

2.3.4 Step four: Design verification – Post-Synthesis simulation ... 46

2.3.5 Step five: Design implementation ... 46

2.3.6 Step six: Design verification – Post-Layout simulation ... 46

2.3.7 Step seven: Device Programming ... 47

2.3.8 Step eight: System verification ... 47

2.4 Simulation environment ... 47

2.4.1 Makefile ... 48

2.4.2 Cadence simulator... 48

2.4.2.1 Design compile and ncvhdl ... 49

2.4.2.2 Design Elaboration and ncelab... 50

2.4.2.3 Design Simulation and ncsim... 51

2.4.2.4 Design simulation GUI and SimVision ... 51

2.5 Architecture of testbench environment ... 53

III

2.5.1 Tb script ... 54

2.5.2 Testbench code... 56

2.5.2.1 Data-in vectors for router’s ports... 58

2.5.2.2 Data-out vectors for router’s ports... 60

2.5.2.3 Configuration of router and external spw_itf ... 60

2.5.3 Registers of router_core block... 62

2.5.4 Registers of spw_itf block ... 65

2.5.5 Router Table programming ... 65

2.5.5.1 Router Table writing access ... 67

2.5.5.2 Router Table reading access... 68

2.5.6 Router internal ports settings... 68

3. CHARACTERIZATION OF THE SPACEWIRE ROUTER IP ON ACTEL TECHNOLOGY ... 71

3.1 Target technology... 71

3.1.1 Differences between RTAX-S and Axcelerator... 72

3.1.1.1 RTAX-S modifications for SEU immunity ... 72

3.1.1.2 Enhancements for improved SEU immunity... 73

3.2 Axcelerator Starter Kit and Evaluation Board ... 74

3.2.1 Axcelerator Evaluation Board... 75

3.2.1.1 Clock circuits of Evaluation board ... 76

3.2.1.2 LED device connections of Evaluation Board... 76

3.2.1.3 Push buttons device connections of Evaluation Board... 77

3.2.1.4 LVDS connections of Evaluation Board ... 77

3.2.1.5 Prototyping headers of Evaluation Board... 78

3.3 Axcelerator FPGA... 78

3.3.1 Key features ... 79

3.3.2 Antifuse technology ... 80

3.3.3 Device architecture... 80

3.3.4 Embedded memory ... 82

3.3.5 I/O logic ... 82

3.3.6 Routing... 83

3.3.7 Global Resources ... 84

3.4 Characterization of the router into target device ... 85

3.4.1 Precision RTL Synthesis ... 85

3.4.2 Study of porting problems... 87

3.4.2.1 Limitation of the Router Table ... 87

Contents

IV

3.4.2.2 Clock management and use of PLLs ... 88

3.4.2.3 Reset push button ... 91

3.4.2.4 Service logic for the host port ... 93

3.4.2.5 LVDS buffers ... 97

3.4.2.6 Router host port’s FIFOs loopback ... 99

3.4.3 Top level synthesis... 100

3.4.4 Design implementation with Actel Designer ... 103

3.5 Design and realization of PCB daughter board... 107

3.5.1 Cadence OrCAD ... 110

4. VERIFICATION AND TESTS RESULTS... 116

4.1 Testbench specific for top level design... 116

4.1.1 Scenarios used for verification... 118

4.1.1.1 Scenario 1 (Basic) ... 119

4.1.1.2 Scenario 2 (Stressing)... 122

4.2 Daughter board tests... 123

4.3 System verification test set-up... 125

CONCLUSIONS... 127

BIBLIOGRAPHY... 129

V

Figure 1.1: SpaceWire cable construction... 6

Figure 1.2: SpaceWire connector contact identification. ... 7

Figure 1.3: SpaceWire cable assembly... 8

Figure 1.4: LVDS signalling levels. ... 9

Figure 1.5: LVDS operation with driver and receiver... 10

Figure 1.6: Data-Strobe (DS) encoding... 11

Figure 1.7: SpaceWire data characters. ... 13

Figure 1.8: SpaceWire control characters. ... 13

Figure 1.9: SpaceWire control codes... 14

Figure 1.10: Parity coverage... 14

Figure 1.11: Data and Strobe signals on link start... 15

Figure 1.12: Link restart. ... 18

Figure 1.13: Packet format. ... 18

Figure 1.14: An example network. ... 20

Figure 1.15: Wormhole routing... 21

Figure 1.16: Header deletion. ... 22

Figure 1.17: Header deletion across multiple switches. ... 22

Figure 1.18: SpaceWire network example. ... 24

Figure 1.19: Example SpaceWire network routing table contents. ... 25

Figure 1.20: Example SpaceWire network with regional addressing. ... 26

Figure 1.21: Group adaptive routing. ... 27

Figure 1.22: Logical address and Protocol identifier. ... 28

Figure 1.23: Write command/acknowledge sequence... 30

Figure 1.24: GRSPW2 block diagram... 33

Figure 1.25: STAR-Dundee SpW router IP block diagram... 34

Figure 1.26: SpaceWire UK Codec and Switch Core. ... 37

Figure 1.27: CESR Open SpaceWire block diagram. ... 38

Figure 2.1: IP database directory structure... 39

Figure 2.2: Architecture of the SpW router macrocell. ... 41

Figure 2.3: Architecture of the SpW interface macrocell... 43

Figure 2.4: Actel Design Flow used in this project. ... 44

Figure 2.5: Inputs and outputs of ncvhdl. ... 50

Index of Figures

VI

Figure 2.6: Inputs and outputs of ncelab. ... 50

Figure 2.7: Inputs and outputs of ncsim. ... 51

Figure 2.8: GUI of a simulation under SimVision environment... 52

Figure 2.9: Architecture of testbench environment... 53

Figure 2.10: Installation of a scenario (option 1). ... 54

Figure 2.11: Comparison of testbench results with the reference scenario (option 2)... 55

Figure 2.12: Update of a scenario with current results (option 3). ... 55

Figure 2.13: Creation of a new scenario with current inputs and results (option 4)... 56

Figure 2.14: Main blocks used in testbench. ... 57

Figure 2.15: Schematic view of tb_router in case of ports equal to 8. ... 57

Figure 3.1: Axcelerator Starter Kit... 74

Figure 3.2: Actel Evaluation Board... 75

Figure 3.3: Axcelerator Interconnect elements (left) and architecture comparison (right). 80 Figure 3.4: AX C-cell and R-cell. ... 81

Figure 3.5: AX device architecture (AX1000 shown)... 81

Figure 3.6: I/O cluster arrangement... 83

Figure 3.7: AX routing structures... 84

Figure 3.8: Precision RTL application window. ... 86

Figure 3.9: Global network distribution on the AX2000 (left ) and PLL group (right). ... 88

Figure 3.10: Clock network access architecture... 89

Figure 3.11: Clock distribution through PLLs (left) and the SmartGen GUI (right). ... 90

Figure 3.12: Brute Force Synchronizer (BFS). ... 91

Figure 3.13: Synchronization of an active low reset with BFS (left) and reset release waveforms (right). ... 92

Figure 3.14: Push buttons output waveforms in different experiments (on left: vertical scale - 1V/div, horizontal scale - 25μV/div; on right: vertical scale - 500mV/div, horizontal scale - 100μV/div). ... 93

Figure 3.15: Schematic view of host_led_manager block. ... 95

Figure 3.16: Architecture of the host_led_manager macrocell... 95

Figure 3.17: Axcelerator LVDS board-level implementation... 97

Figure 3.18: Association between internal AX500 I/O banks and external headers bank on Actel Evaluation Board. ... 98

Figure 3.19: Headers selected for SpW ports (real picture on left and schematic view on

right). ... 99

VII

Figure 3.20: Architecture of the host port’s FIFOs loop. ... 100

Figure 3.21: RTL schematic view of top level design in Precision RTL. ... 101

Figure 3.22: Actel Designer application window... 103

Figure 3.23: Physical view of regions on ChipPlanner. ... 105

Figure 3.24: Top view of external LVDS driver and receiver and corresponding logic diagram. ... 107

Figure 3.25: Layout architecture for external LVDS buffer of a SpW router’s port on daughter board. ... 108

Figure 3.26: Architecture of the circuitry for SpW router’s ports on daughter board... 109

Figure 3.27: Application windows of OrCAD Capture CIS (on left) and... 110

Figure 3.28: OrCAD Capure’s schematic about LVDS page... 111

Figure 3.29: OrCAD Capure’s schematic about POWER page. ... 112

Figure 3.30: Layout of daughter board with a TOP view and all layer overlapped. ... 115

Figure 3.31: Top view of the realized daughter board. ... 115

Figure 4.1: Main blocks used in testbench specific for top-level design. ... 116

Figure 4.2: Architecture of tb_router_on_actel. ... 117

Figure 4.3: LVDS signals of a differential pair... 124

Figure 4.4: Test environment for two ports loopback on daughter board. ... 125

Figure 4.5: System set-up where daughter board is mounted onto the Evaluation Board. 126

I ^{NDEX OF} T ^ABLES

VIII

Table 1.1. SpW protocol layers vs. ISO/OSI layers. ... 31

Table 2.1: 9-bit binary code of text line’s data file. ... 59

Table 2.2: Data coding for input and output vectors of router ports. ... 59

Table 2.3: Example of a packet in a data-in file, expressed with a set of text lines... 59

Table 2.4: Example of a packet in a data-out file read from a port and expressed with text lines... 60

Table 2.5: List of commands used for spw_if and router’s configuration in datainconf.txt file... 62

Table 2.6: Control register of a router_core’s port... 62

Table 2.7: Status register of a router_core’s port. ... 63

Table 2.8: TimeCode register of router_core... 64

Table 2.9: Programming router register of router_core... 64

Table 2.10: Routing switch space addressing of router_core. ... 65

Table 2.11: Data structure of a Router Table location. ... 66

Table 2.12: 9-bit binary code for data port setting. ... 69

Table 3.1: Major architectural differences between Axcelerator and RTAX-S. ... 74

Table 3.2: LED/Device connection. ... 77

Table 3.3: Push Button/Device connection. ... 77

Table 3.4: LVDS connections. ... 77

Table 3.5: Header connections. ... 78

Table 3.6: Axcelerator Family characteristics... 79

Table 3.7: Pinout for SpW router ports’ signals... 99

Table 3.8: Clock and design constraints for critical signals of the project... 102

Table 3.9: Association between I/O ports and package pins... 104

Table 3.10: Timing results with static timing analysis after place-and-route process. ... 106

Table 3.11: Results of the device utilization (AX500) for the 3-link SpW router. ... 106

Table 3.12: Bill of components for daughter board... 113