Development on Deep N Well MAPS in a 130 nm CMOS Technology and Beam Test Results on a 4k-Pixel Matrix with Digital Sparsified Readout

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Giuliana Rizzo

INFN and University, Pisa on behalf of SLIM5 Collaboration

Development on Deep N Well MAPS in a 130 nm CMOS Technology and

Beam Test Results on a 4k-Pixel

Matrix with Digital Sparsified Readout

2008 IEEE Nuclear Science 2008 IEEE Nuclear Science

Symposium Symposium

Dresden, October 19-25 Dresden, October 19-25

2008 2008

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Outline

• Deep NWell Monolithic Active Pixel Sensor (MAPS) design concept

 the APSEL series chips

• Performance of the latest chip

• Preliminary Testbeam results

• Conclusions & Perspectives

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Deep NWell MAPS design

• Full in-pixel signal processing chain exploiting triple well CMOS process

• Deep NWell as collecting electrode

with most of the front-end overalapped in the pwell

• Can extend collecting electrode

(charge preamp --> gain independent of sensor cap. )

• Allow design with small “competitive”

nwells for PMOS inside the pixel.

Area kept to a minimum:, they steel signal to the main DNW electrode.

• Fill factor = DNW/total n-well area

~90% in present design • Pixel structure compatible with data sparsification architecture

PRE SHAPER DISC LATCH

competitive nwell Deep nwell

• CMOS MAPS for future vertex detectors: thin (OK!) but also need to be fast (i.e. continuous background rate @ SuperB Factory several MHz/cm2)

• New approach in MAPS design: hybrid-pixel-like structure to

improve the readout speed: APSEL chip series

SLIM5 Collaboration - INFN &

Italian University

50m pixel pitch

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APSEL Generations

Proof of principle (APSEL0-2)

• first prototypes realized in 130 nm triple well ST-Microelectronics CMOS process

APSEL3

• Pixel cell optimization (50x50 m

²

)

– Increase S/N (15-30)

– reduce power dissipation x2 (30 W/ch)

• Average Signal for MIP (MPV) = 1000e-

• ENC ranging from 30 to 60 e- in the different front-end versions

• Details on the different front-end versions in L. Ratti talk (N44-6) APSEL4D

• First MAPS matrix with in-pixel

sparsification and timestamp info on hit.

• 4K pixel matrix with data driven readout architecture

– --> LV1 trigger system with tracks info based on Associative Memories

• Pixel cell & matrix implemented with full custom design and layout

• Perifery readout logic synthetized in std-cell from VHDL model

APSEL4D

32x128 4k pixel matrix for beam test sub 11/2007- rec 3/2008

90

Sr electrons APSEL3T1 M2

Landau mV

S/N=23

Cluster signal (mV)

Noise events properly normalized

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Data lines in common

2 MP private lines MP 4x4

pixels

Periphery readout logic

Column enable lines in common

Periphery readout logic:

• Register hit MP & store timestamp

• Enable MP readout

• Receive, sparsify, format data to output bus

32x128 pix - 50 m pitch perif & spars logic

APSEL4D: 4096 pixel matrix with data driven sparsified readout + timestamp Implemented architecture needs to minimize:

• In-pixel PMOS (competitive nwells) to preserve the collection efficiency.

• digital lines for point to point connections to allow scalability to large matrix and to reduce possible cross talk with the sensor underneath.

• Matrix subdivided in MacroPixel (MP=4x4pixels) with point to point

connection to the periphery readout logic

Readout tests

• All readout functionality tested with a dummy matrix implemented on chip.

• The readout is working properly even with 100%

occupancy.

• Three clocks are used: the BCO clock, used for the timestamp counter, a faster readout clock, and a slow control clock.

• Test performed with RDCLK up to 50 MHz

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APSEL4D Results Noise distribution

mV

Average Noise 9 mV

Offset distribution

mV

Threshol d dispersi on 9 mV

55Fe 5.9 keV peak (all pixels in matrix)

1390 THRDAC = 230mV

THR(DAC)

Gain distribution (all pixels in matrix)

mV/fC Gain = 860

mV/fC

Spread = 6%

• New cross talk effects observed in APSEL4D, correlated with the readout activity, still under investigation. A new version of the chip will be submitted in Nov ‘08 with more diagnostic features and modifications introduced to reduce some potential source of digital crosstalk.

• By reducing the digital voltage from 1.2 to 1 V able to reduce this effect still being able to operate the matrix and the readout.

• All results shown have been obtained with the reduced digital voltage.

• Noise and threshold from threshold scans

–Average Threshold dispersion inside matrix: 8mV (57e-)

– Average pixel noise: 10.5 mV (ENC = 75e-) with 20%

dispersion inside the matrix

• Gain Calibration (

⁵⁵Fe-5.9 keV peak)

–<Gain> = 890 mV/fC ± 6%

– Obtained by differentiating the

integral spectrum since no analog

info available.

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SLIM5 Beam test

• SLIM5 Beam test 3-16 Sep. 2008 @ CERN. Main goals:

– APSEL4D DNW MAPS matrix resolution & efficiency

– Thin (200 m) striplets module with FSSR2 readout chips – First demostration of LVL1 capability with silicon tracker

information sent to Associative Memories

• M.Piendibene talk N36-4

APSEL4D chip 10 mm² active area

• A few numbers:

• Maps readout clock 20 MHz

• DAQ rate 30 kHz

• 90 M events on disk (40 Gb)

• Data analysis ongoing

APSEL4D chip

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Competitive nwells 0.5 MIP

DNW MAPS Hit Efficiency • Measured with tracks reconstructed with the reference telescope

extrapolated on MAPS matrix

• Competitive nwells present in pixel cell can steel charge reducing the hit efficiency

– Fill factor DNW/total n-well area ~ 90 % in present design

• Room for improvements with a different design of the sensor (multiple collecting electrodes around competitive nwells)

• Fast device simulation developed for cell optimization

– ionization, charge diffusion, front-end response included – Good agreement simulation vs efficiency data, although

simulation still overestimates total cluster collected charge

• MAPS hit efficiency up to 90 % with threshold @ 450 e- (~

4  _noise+2  _thr_disp)

• 300 and 100  m thick chips give similar results

• Efficiency on chip 21 at low threshold under investigation

Reminder on Pixel Layout

DNW sensor

0.5 MIP

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Efficiency inside the pixel cell

• Efficiency inside the pixel cell (data) correlated with layout. As expected:

– Collecting electrode region has higher effi  max in region 5

– Perifery has lower efficiency especially in regions with competitive nwells

• Very preliminary study: Efficiency map shown is diluted from error on track impact point extrapolation: cross feed among cells.

• Still need to deconvolve this effect

Chip 23 – 100 um Thr @ 0.67 MIP

m

Efficiency inside pixel cell

1 2 3

4 5 6

7 8 9

DNW sensor

1 2 3

4 5 6

7 8 9

Competitive nwells

Preliminary

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Efficiency across matrix

• Efficiency uniform across the matrix

– Gain dispersion ~ 6%  similar dispersion in the effective threshold applied on each pixel.

– Efficiency spread of about 10% expected among pixels.

cm

8x16 pixels/bin

Chip 23 – 100 um thick Threshold 0.67 MIP

Global Efficiency MAPS

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MAPS Resolution Residual (=SP_meas-SP_trk) after alignment

• From the width of residual plot extract intrisic resolution

according to:

• Results consistent with 50 m pitch with digital readout

(50/sqrt(12) = 14.4 m)

 _res_x=16 m

cm

MAPS Intrinsic Resolution vs Threshold

x Coordinate y Coordinate

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Conclusions & Perspectives

• Good progress achieved on DNW MAPS design

– S/N between 15-30 with different front-end versions.

– Power consumption reduced to ~30 W/ch .

• A first MAPS matrix with in-pixel sparsification and timestamp information for hits fully characterized and tested with beams with very encouraging results:

– Threshold dispersion across matrix ~ 60 e- – Pixel Noise ENC = 75 e-

– Hit efficiency up to 90% (sensor design not optimized yet!) with good uniformity across the matrix.

– Intrisinc resolution ~ 14 m compatible with 50 m pitch and digital readout.

• Next steps:

• Within the SuperB effort build a prototype multichip MAPS module based on an evolution of the APSEL4D DNW matrix (optimized pixel cell and larger area).

• Within the new VIPIX Italian Collaboration (Vertically

Integrated PIXel) realize 3D MAPS with the Chartered –

Tezzaron 130 nm CMOS process (Vertical Scale Integration)

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1Università degli Studi di Pisa, ²INFN Pisa, ³Scuola Normale Superiore di Pisa,

4Università degli Studi di Pavia, ⁵INFN Pavia,

6Università degli Studi di Bergamo,

7INFN Trieste and Università degli Studi di Trieste

8INFN Bologna and Università degli Studi di Bologna

^5,6

, G. Traversi

^5,6

,

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Backup

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 Sustantial redesign of the pixel cell in the APSEL3 chips with improved S/N and reduced power consumption (30 uW/ch)

 Major source of digital crosstalk (capacitive coupling with sensor

underneath) reduced inserting a metal shield between digital lines and sensor

 Some digital crosstalk still present in the APSEL3 series, Under investigation.

APSEL3 chips results

90

Sr electrons

Landau mV

S/N=23

Cluster signal (mV)

Noise events properly normalized

Fe55 5.9 keV calibration peak ( 1640 e-)

Chip 6 T1-M2 50m pixel pitch

Average Signal for MIP (MPV) = 1000e-

3x3 matrix, full analog output

Front- end

ENC (e-)

Gain (mv/fC)

S/N (MIP)

T1 43-64 860 16-23

T2 31-40 1000 27-33

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An example of sensor optimization

DNW collecting electrode Competitive Nwells

3x3 MATRIX

present sensor geom

Satellite nwells connected to central DNW elect

3x3 MATRIX sensor optimized

Optimize sensor geometry for charge collection efficiency with fast simulation developed:

• Locate low efficiency region inside pixel cell

• Add ad hoc “satellite” collecting electrodes

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Collected charge data vs simulation

• Simulation overestimates by

~ 10 % the collected charge measured on test structure with analog output

• Need more tuning

Collected charge in cluster seed pixel

black line – fit to data MPV=148 mV

Red line - fit to simulation MPV=164 mV

3x3 cluster total collected charge

black line – fit to data MPV=77 mV

Red line - fit to simulation MPV=85mV

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APSEL3T1 pixel cell

DNW + NMOS Analog section

PMOS Analog section

Digital

section Nwell satellite

collecting electrodes

50  m

Sensor geometry B Sensor geometry A

50



m

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APSEL4D cell layout

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DNW MAPS Efficiency

• Extrapolate on MAPS DUT tracks reconstructed with the reference telescope:

– Evaluate number of tracks intersecting the DUT

– Evaluate number of clusters associated with tracks from residual plot:

RES(=SP_meas-SP_expected) peaks for track hits.

Noise hits Tracks hits

cm

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Absolute gain calibration from Fe55 source

• In APSEL4D no analog information is available and the calibration peak is reconstructed from the differential rate as a function of the discriminator threshold.

• Can calibrate the single pixel gain …quite long procedure though!

• 5.9 keV line (1640 e-) with charge totally collected by a single pixel



PWELL NWELL

P^- EPI-LAYER

P⁺⁺ SUBSTRATE PWELL

INCIDENT PHOTONS

Charge entirely collected

DEPLETION REGION Charge

only partially collected by single pixel



When the pulse height info is available gain is extracted from the position of the calibration peak

Fe55 Calibration Peak

Fe55 5.9 keV calibration peak

Pixel signal (mV) Integral rate

Differential rate High thr.

Fe55 ]peak

High thr.

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G. Rizzo 2008 IEEE Nuclear Science Symposium - Dresden, October. 19 – 25 2008 22

From APSEL2 to APSEL3

• Cross talk between digital lines and substrate

– Requires aF level parasitic extraction to be modeled

• Relatively small S/N ratio (about 15)

– Especially important if pixel eff. not 100%

• Power dissipation 60 W/pixel

– Creates significant system issues

M1 M2 M3 M5 M6

M4 Analog routing

(local)

Digital routing (local/global) Shield

(VDD/GND)

APSEL3 Redesigned front-end/sensor

APSEL3D Digital lines shielding

Optimize FE Noise/Power:

• Reduce sensor capacitance (from 500 fF to ~300 fF) keeping the same collecting electrode area

– reduce DNW sensor/analog FE area (DNW large C) – Add standard NWELL area (lower C) to collecting

electrode.

• New design of the analog part

Optimize sensor geometry for charge collection efficiency using fast simulation developed:

– Locate low efficiency region inside pixel cell – Add ad hoc “satellite” collecting electrodes

APSEL3 Power=30 W/pixel: Perfomance

APSEL2 issues

APSEL3 expected performance

FE Version Geom .

ENC

(PLS) 

^(@5

^

^ ^S/N

APSEL2

^data

A 50 e- 88.7% 14 APSEL3

Transc.

A B

41 e- 41 e-

93.6%

99.4%

16 18 APSEL3

Curr. Mirror

A B

31 e- 31 e-

98.6%

99.9%

22

24

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• Basic R&D on DNW CMOS MAPS started in 2004 within the SLIM5 Collaboration.

– Several Italian Institutions involved in the project:

• BO, PI (coordination), PV-BG, TO, TN, TS.

– R&D project supported by the INFN and the Italian Ministry for Education, University and Research.

SLIM5- Silicon detectors with Low Interactions with Material

Realize a demonstration thin silicon tracker with LVL1 trigger capabilities:

• CMOS monolithic active pixels

• Thin strip detectors on high resistivity silicon

• Associative memory system for track trigger

• Low mass mechanical support and services

SLIM5 Purpose: develop technology for thin silicon tracker systems (sensor/

readout/ support structure/ cooling) crucial to reduce multiple scattering effects for future collider experiments (SuperB, ILC)

SLIM5

Project

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MAPS Radiation Hardness

• Expected Background @ SuperB Layer0: 5 MHz/cm2

– Dose ~ 1Mrad/yr

– Equivalent fluence ~ 1x10

¹²

n

eq

/cm

²

/yr

• CMOS redout electronics (deep submicron) rad hard

• MAPS sensor - Radiation damage affects S/N

• Non-ionizing radiation: bulk damage cause charge collection reduction, due to lower minority carrier lifetime (trapping)

 fluences 10

¹²

n

_eq

/cm

²

affordable, 10

¹³

n

_eq

/cm

²

possible

• Ionizing radiation: noise increase, due to higher diode leakage current (surface damage)

 OK up to 20 Mrad with low integration time (10 s) or T operation < 0

^o

C, or modified pixel design to improve it

• Irradiation test performed on several MAPS prototypes, with standard nwell sensor, indicate application for SuperB is viable.

• APSEL chips irradiation started

Results from standard nwell MAPS prototypes

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TID tests (-rays up to 1.1 Mrad) have been performed for the first

time on DNW-MAPS, conceived for particle tracking in HEP experiments at the next high luminosity colliders

DNW MAPS first irradiation tests

Change in charge sensitivity of the order of 10%

mainly due to radiation induced narrow channel effects in some critical points of the preamplifier and the shaper and to leakage current from the detector

More significant increase in equivalent noise charge ~ 25%

mainly due to 1/f noise increase in the preamplifier input device and in the parallel noise contribution from the preamplifier feedback NMOS and from the detector

in order to avoid excessive flicker noise increase, use of radiation hard techniques (e.g. ELT transistors) may be required

parallel noise issue may be addressed by using smaller peaking times

Future plans include tests with higher TIDs, rad-hard characterization of the most recent versions of the DNW-MAPS, and investigation of bulk damage effects by neutron and proton irradiation

L. Ratti - RADECS 2008

8th European Workshop on Radiation Effects on

Components and Systems

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Effects on equivalent noise charge

30 40 50 60 70 80 90 100 200

4 10^-7 6 10^-7 8 10^-7 10^-6 3 10^-6 before irradiation - measured

1100 krad - measured after annealing - measured

ENC [e- rms]

Peaking time [s]

channel thermal noise in the input device

flicker noise in

the input device parallel noise in the feedback MOSFET

p leak wp, 3 p

F wp, 3 1

p in f, 2 2 T p

in ws, 1 2 T

2

C A A t A S t A S t

t S 1

A C

ENC  

^^fn^

 

affected by ionizing radiation

parallel noise in the

detector leakage

DNW-MAPS (900 m

²