Beam Test Results of Different Configurations of Deep N-well MAPS Matrices Featuring in Pixel Full Signal Processing.

Beam Test Results of Different Configurations of Deep N-well MAPS Matrices Featuring in Pixel Full Signal Processing.

Eugenio Paoloni for the VIPIX collaboration

University and INFN, Pisa, Italy (e-mail: eugenio.paoloni@pi.infn.it) November 16, 2009

Abstract

We report on further developments of our proposed design approach for a full in-pixel signal processing chain of deep N-well (DNW) MAPS sensor, by exploiting the triple well option of a CMOS 130 nm process.

We implemented two different versions of the analog circuits and we optimized the collecting electrode geometry to improve the charge collection efficiency.

We will present the simulation tool that we developed to optimize the collecting electrode geometry and the criteria we adopted to choose the best ones. Two different geometries of the collecting electrode have been implemented in 3 × 3 matrices with analog outputs for each pixel.

The results of the characterization of the various versions of pixel matrices with a pion beam of 120 GeV/c at the SPS H6 CERN facility will be presented, comparing the charge collection efficiencies. The perfor- mances of an “apsel3T1” chip irradiated with a dose up to 10 MRad (Co

) was also measured. Comparison will be presented among the irradiated and the new chip showing the impact of radiation damages on tracking efficiencies.

CMOS Monolithic Active Pixel Sensors (MAPS) are thin tracking devices for charged particles [1]. MAPS are considered promising candidates for the vertex detectors at future colliders, such as SuperB or ILC, being able to match the stringent requirements on spatial resolution, read-out speed and power consumption posed by the physics goals and by the setup of these experiments.

The authors are proponents of a recently implemented approach to the design of CMOS MAPS that exploit the triple well STM 130 nm CMOS technology.

The detector makes use of a set of deep N-type well (DNW) buried in a thin P-type epitaxial layer (P-EPI) to collect the minority carriers generated by the incident particle along its path in the P-EPI.

A full analog signal processing chain and a digital part is realized at the pixel level ( 50 µm × 50 µm). The analog readout is made by a charge integrator whose input is connected to the DNW followed by an RC-CR shaper and a discriminator. The asynchronous discriminated signal is stored by a latch till the peripheral digital read-out is ready to process it.

Several prototype chips (the apsel series) have been realized including single pixel cells, small pixel matrices with a simple sequential digital readout, small 3 × 3 pixel matrices with analog readout and a 4096 pixel matrix with digital sparsified read-out.

Results on these prototypes have been presented at the 2005, 2006, 2007 and 2008 IEEE NSS [2–5], proving that the new design proposed for DNW MAPS is viable with a good sensitivity to minimum ionizing particles.

We are going to report on new results obtained with several small 3 × 3 matrices implementing an analog readout for each pixel. These results are the outcomes of a beam test we performed this year in July at the SPS H6 beam-line at CERN.

Charge collection and tracking efficiencies was measured using a 120 GeVc pion beam and the SLIM5 tele- scope.

Four different combinations of pixel layout and analogical read-out chain were characterized. The charge collecting efficiency of the DNW depends on its fill factor (i.e.: the ratio of the DNW area to the pixel cell area) and its shape.

The DNW fill factor is limited by the presence of “competitive” N-type wells (CNW) whose size is dictated by the necessity to realize at the pixel level all the PMOS of the analog readout chain and of the digital control circuits.

The shape of the DNW and of the CNW have been designed optimizing the charge collection efficiency while keeping the collector electrode capacitance near its minimum. We simulated the device with a fast Monte Carlo program developed by us that model the straggling in the thin P-EPI following Bichsel [6] and that simulates the thermal diffusion of the minorities carriers using discrete random walks.

Two different shapes of the sensor have been identified and implemented in the chips: the collecting electrode of the first one has a single central “T” shaped DNW (type M2), the second one has a rectangular DNW core connected to additional satellite N-well (type M1).

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Two different analog chains was also realized in the chips. Beside the standard optimum signal processing chain ( charge integrator, CR-RC shaper, discriminator) implemented in the 3T1 with DNW type M1 and M2 (3T1M1, and 3T1M2), a shaper less chain was also implemented in the chips series “5T” (5TM1 and 5TM2).

The scaling to larger matrix sizes of the fast read-out architecture implemented in the previous chip [5]

dictates to remove the shaper stage in the pixel cell to make room for additional routing toward the peripheral logic, moreover in the shaper less cell the pitch could be reduced to 40 µm.

The 9 analog outputs of each 3 × 3 matrix was read with a custom made VME board hosting a battery of 16 10 bit FADC clocked at 100 MHz controlled by an FPGA. The main difficulty of the test relies in the extremely small size of the 3 × 3 matrices (150 µm × 150 µm) with respect to the beam spot size achievable with H6 beam line (order of several cm

).

To solve this problem we used the SLIM5 silicon strip telescope as main tracking device and we developed an on-line area trigger to select the very small subset of events in which a track intersect a fiducial area of 500 µm × 500 µm around the central pixel of the matrix under test.

Off line alignment and track reconstruction enabled us to apply tighter geometrical requirements to select a smaller unbiased sample suitable for our characterization studied.

We obtained the distribution of the total charge collected by the cluster. It exhibits a Landau distribution with most probable value 1038 ± 20e

for the matrix 3T1M1 and 931 ± 18e

for the 3T1M2.

We also measured the tracking efficiency as a function of the threshold level of the discriminator.

Test on a 3T1 chip irradiated with 10 MRad and annealed was also performed. We observed a 30% increase in equivalent noise charge and a 4% decrease of the analog chain gain.

Results for the 5T matrices are still under study and will be reported at the conference.

References

[1] R. Turchetta et al., “Nucl. Instrum. Methods, A458 (2001) 677.”

[2] G. Rizzo et al., “Novel monolithic active pixel detector in 0.13 µm triple well CMOS technology with sensor level analog processing”, 2005 IEEE Nuclear Science Symposium, Puerto Rico, October 24-27, 2005.

[3] F. Forti et al., “Development of 130 nm Monolithic Active Pixels with In-Pixel Signal Processing”, L. Ratti et al.; “Design and Performance of Analog Circuits for DNW-MAPS in 100-nm-scale CMOS Technology”, 2006 IEEE Nuclear Science Symposium, San Diego (USA), October 30-November 2, 2006

[4] G. Rizzo et al., “Recent Development on Triple Well 130 nm CMOS MAPS with In-Pixel Signal Processing and Data Sparsification Capability”, 2007 IEEE Nuclear Science Symposium, Honolulu, Hawaii (USA), October 27-November 3, 2007

[5] S. Bettarini et al., “Development on Deep N Well MAPS in a 130 nm CMOS Technology and Beam Test Results on a 4k-Pixel Matrix with Digital Sparsified Readout “, 2008 IEEE Nuclear Science Symposium, Dresden (Germany), October 19-25, 2008

[6] H. Bichsel, “Straggling In Thin Silicon Detectors,” Rev. Mod. Phys. 60 (1988) 663.

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