Recent Development on Triple Well 130 nm CMOS MAPS with In-Pixel Signal Processing and Data
Sparsification Capability
Giuliana Rizzo for the SLIM5 Collaboration University and INFN, Pisa, Italy
E-mail: rizzo@pi.infn.it
Abstract— A different approach to the design of CMOS MAPS has recently been proposed. By exploiting the triple well option of a CMOS commercial process, a deep nwell (DNW) MAPS sensor has been realized with a full in-pixel signal processing chain: charge preamplifier, shaper, discriminator and a latch.
This readout approach beeing compatible with data sparsification will improve the redout speed potential of MAPS sensors. The first protoype chips, realized with STMicroelectronics 130 nm triple well process, proved the new design proposed for DNW MAPS is viable with a good sensitivity to photons from55Fe and electrons from 90Sr. We report on extensive tests performed to characterize the last generation of the APSEL chips based on the DNW MAPS design. Small 3x3 pixel matrices with full analog output have been tested with radioactive sources to characterize charge collection. Pixel noise equivalent charge (ENC) of 50 e- and Signal-to-Noise ratio for MIPs of about 14 have been measured. Improved pixel noise and reduced threshold dispersion (about 100 e-) have been measured in the 8x8 matrix with a sequential readout. Based on the new DNW MAPS design a dedicated fast readout architecture to perform on-chip data sparsification is currently under development. The aim is to incorporate in the same detector the advantages of the thin CMOS sensors and similar functionalities as in hybrid pixels.
APSEL2D is a first prototype chip that includes the first blocks of the data driven architecture under development.
I. SUMMARY
Vertex detector for experiments at future colliders such as SuperB or ILC will need to fulfill very stringent requirements on position resolution, readout speed, material budget and radi- ation tolerance. New CMOS Monolithic Active Pixel Sensors (MAPS) are a promising candidate for such application [1]:
they incorporate on the same substrate the readout electronics and a very thin sensor, with the possibility to reduce the detector material budget down to 50µm. The MAPS device uses an n-well/p-epitaxial diode to collect, through thermal diffusion, the charge generated by the impinging particle in the thin epitaxial layer underneath the readout electronics. In this technology the signal collected is only a few hundreds of electrons, for typical p-epitaxial thickness of about 10µm.
CMOS MAPS prototypes have been developed by several groups over the last few years. These designs follow the very simple readout scheme already adopted for imaging applications, based on the use of only three transistors on the pixel cell (3T), with a sequential readout. Although these prototypes have shown excellent tracking performance, their
Fig. 1. Cross section of the triple well active pixel sensor with in-pixel signal processing.
readout speed, limited by the sequential processing, is one of their major limitations for future applications.
A different approach to the design of CMOS MAPS has recently been proposed to improve the readout speed potential of these devices and at the same time to increase the sensitive element area. By exploiting the triple well option of CMOS commercial processes, a full signal processing chain has been implemented at the pixel level (charge preamplifier, shaper, discriminator and a latch), building a monolithic pixel with a readout scheme easily compatible with data sparsification.
The concept of the new design is illustrated in Fig. 1: the deep n-well (DNW), of the triple well process, is used as a charge collecting electrode and also contains part of the front- end stage, which is physically overlapped with the area of the sensitive element. In this way the collecting electrode can cover a large fraction of the elementary cell, maximizing the fill factor, and at the same time more room is available to develop a more complex in-pixel readout electronics.
Two prototype chips (APSEL series) have been realized with the STMicroelectronics, 130 nm, triple well technology, including single pixel cells and a small pixel matrix with a simple sequential readout. Results on these prototypes pre- sented at the 2005 and 2006 IEEE NSS [2] [3] proved the new design proposed for DNW MAPS is viable with a good sensitivity to photons from55Fe and electrons from90Sr.
In this paper we report on test performed to characterize the next generation of DNW MAPS prototypes: the APSEL2
Fig. 2. Cluster signal for electrons from a beta90Sr source. Landau most probable value corresponds to 700 e- (pixel gain calibration = 530 mV/fC)
chips. They implement the design improvements suggested from the test of previous APSEL chips and include more diagnostic features. In particular a partial redesign of the analog circuit has been realized to reduce significantly the threshold dispersion without increasing the noise figure. The major source of crosstalk between digital signal and the analog circuit, observed in the APSEL1 chip, has been eliminated with a proper dimensioning of the ground lines. With this new pixel design we realized three APSEL2 chips with different test structures.
APSEL2T includes 3x3 pixel mini-matrices with full analog information to properly characterize the charge collection.
APSEL2M contains a 8x8 matrix with digital output and sequential readout. For diagnostic pourpose the analog out- put and an injection capacitance, for channel calibration, is available on selected pixels inside the matrix.
Based on the new DNW MAPS design a dedicated readout architecture to perform on-chip data sparsification is currently under development. The aim is to incorporate in the same detector the advantages of the thin CMOS sensors and similar functionalities as in hybrid pixels. The key issues for this development are to minimize logical blocks inside the active area (if realized in “competitive” nwells they steal charge from the DNW sensor) and to reduce to a minimum the digital lines crossing the sensor area (to reduce the residual cross talk effects). APSEL2D is a first prototype chip with the digital readout of a small pixel matrix and the first blocks of the data driven architecture developed.
Detailed response of the APSEL2 sensor to charged particle has been measured, on the 3x3 matrix with full analog output, using electrons from a beta90Sr source. The signal of the 3x3 cluster, surrounding the central pixel matrix, is shown in Fig. 2.
The most probable value of the Landau distribution, used to fit the data, corresponds to a signal of 700 e- collected from a MIP crossing the sensor. The average pixel equivalent noise charge measured is about 50 e- ENC, resulting in a Signal-to- Noise ratio for MIPs of about 14.
Further cluster multiplicity analysis indicates that charge sharing among pixels is limited, with an average cluster size of only 2 pixels, for typical cuts on the seed and the adjacent pixels respectively of 5 and 3 times their noise.
On the 8x8 matrix with digital output the pixel ENC and the threshold are evaluated measuring the hit rate as a function of
Fig. 3. Hit rate as a function of the discriminator threshold for a matrix row.
the discriminator threshold, as shown in Fig. 3. With a fit to the turn-on curve (modified erf function used) we have measured a pixel ENC = 50 e-, with about 15% dispersion, and a threshold dispersion of about 100 e- (300 e- reported in previous version of the matrix).
Although the digital crosstalk due to ground bouncing effects has been eliminated in the new pixel design, during the APSEL2 test we still observed residual crosstalk between digital lines and the sensor. After detailed tests and investi- gations we were able to track all the effects to details of the layout: residual coupling capacitance between digital lines and the sensor (at the level of a few tens to a few hundreds of aF) can cause a significant signal injected in the front-end. To reduce this effects to accetable levels, in the next generation of the APSEL pixel, one of the six metal layers, available in the 130 nm ST process, will be used to insert a shield between the sensor and the digital lines. A test structure with the shield inserted in the pixel design is already in production (due by the end of August 2007). Simulation performed with a more sophisticate tool to extract parasitic capacitance (RaphaelNXT) indicates this is a viable solution to eliminate the crosstalk, though measurements on the test structures in production are needed to confirm the accurancy of the extraction tool.
Optimization of the pixel cell to reduce the total sensor capacitance for a better balance between noise and power con- sumption are under study for the new generation of the sensor.
We also developed a fast device simulation (ionization process and charge diffusion taken into account) to optimize the sensor geometry for improved signal collection. The APSEL3 series chip will be submitted in July 2007.
REFERENCES
[1] R. Turchetta et al., Nucl. Instrum. Methods, A458 (2001) 677.
[2] G. Rizzo et al., ”Novel monolithic active pixel detector in 0.13 µm triple well CMOS technology with sensor level analog processing”, 2005 IEEE Nuclear Science Symposium, Puerto Rico, October 24-27, 2005.
[3] F. Forti et al., ”Development of 130 nm Monolithic Active Pixels with In-Pixel Signal Processing”, L. Ratti et al.; ”Design and Performance of Analog Circuits for DNW-MAPS in 100-nm-scale CMOS Technology”, 2006 IEEE Nuclear Science Symposium, San Diego (USA), October 30- November 2, 2006
