A Novel Monolithic Active Pixel Detector in 0.13 µm Triple Well CMOS Technology with Pixel Level Analog Processing

(1)

A Novel Monolithic Active Pixel Detector in 0.13 µm Triple Well CMOS Technology with Pixel Level Analog Processing

G. Rizzo

^a,∗

, S. Bettarini

^a

, G. Calderini

^a

, R. Cenci

^a

, F. Forti

^a

, M.A. Giorgi

^a

F. Morsani

^a

, L. Ratti

^b,d

, V. Speziali

^b,d

, M. Manghisoni

^c,d

, V. Re

^c,d

, G. Traversi

^c,d

L. Bosisio

^e

aINFN-Pisa and Universit`a di Pisa

bUniversit`a di Pavia

cUniversit`a di Bergamo

dINFN-Pavia

eINFN-Trieste and Universit`a di Trieste

Abstract

We designed and fabricated a novel monolithic active pixel sensor (MAPS), in STMicrolectronics 0.13 µm CMOS technology, exploiting the triple well option to implement, at the pixel level, a more complex signal processor and to increase the size of the charge collecting electrode with respect to previously developed CMOS MAPS. This was possible using the deep n-well, available in triple well technology, as a sensing electrode and placing, in the same physical area, part of the readout electronics. The signal processing chain, implemented in the elementary cell, includes a low noise charge preamplifier, a shaper, a discriminator and a latch.

The first protoype chips have been successfully tested with very encouraging results. In this work we present the performance of the front-end electronics and the response of the sensor to ionizing radiation.

Key words: Monolithic active pixel sensors; MAPS; CMOS pixels; charged particle tracking.

PACS:

1. Introduction

Developed for visible light immaging applications [1], CMOS monolithic active pixel sensors (MAPS) have been recently proven to be suitable as tracking devices for ionizing particles [2–5].

These devices offer several potential advantages with respect to earlier pixel detectors (i.e. hybrid

∗ Corresponding author:

E-mail address: [email protected] (G. Rizzo)

pixel or charge-coupled devices). The integration of the sensor and the readout electronics on the same substrate greatly reduces the detector material budget, reducing multiple scattering and improving spatial resolution, while at the same time simplifying detector assembly. Furthermore in CMOS MAPS the active volume of the sensor is only a few tens of microns thick, so the amount of material could be further reduced by thinning the silicon die with micromachining techniques.

The use of a standard deep submicron CMOS

(2)

R SFF

p epitaxial layer− +

+ + + +

+ R

SFF

deep n−well

Logic section Analog section

n−well VF g m

Vt

p−well

VF g m

PMOS PMOS

NMOS

Elementary cell

NMOS

+

+ +

−

− −

−

− −

−

− +

p substrate+

Fig. 1. Cross section of the monolithic pixel detector with pixel level processing

technology results in high functional density, low power consumption and low fabrication costs. Fur- thermore with respect to charge-coupled devices MAPS have readout electronics integrated at the pixel level, thus avoiding the need to transport the collected charge along the sensor volume to the peripheral electronics. MAPS are more radiation hard and faster with respect to CCDs.

For these reasons CMOS MAPS sensors have been proposed as tracking detectors in future high energy experiments (e.g. ILC, SuperBfactory). All the proposed devices are based on the front-end readout scheme already adopted for visible light imaging [1], which is based on sequential readout and is not compatible with data sparsification.

This is one of the major limitations of conventional MAPS for application in enviroments with high data throughput: readout speed is intrinsically lim- ited for a large detector area.

To address this readout speed issue and increase the sensitive element area we designed and fabricated a novel CMOS MAPS sensor, exploiting STMicroelectronics 0.13 µm triple well CMOS technology (HCMOS9GP, through the Circuit Multi-Projects company) to integrate in the elementary cell a more complex signal processor.

In the MAPS device presented in this work we implemented at the pixel level the standard processing chain used for capacitive detectors (charge preamplifier, shaper, discriminator), described in section 2 and shown schematichally in Fig. 1. The proposed readout scheme is compatible with already available architectures performing sparsified readout at the elementary cell level. This feature

will be implemented in future developement of our device with the aim of overcoming the readout speed limitation of conventional MAPS.

The basic design features of the new sensor are reviewed in the next sections and preliminary studies of the physical device simulation are re- ported. Front-end electronics characterization and response of the sensor to ionizing radiation are presented to demonstrate the full functionality of the device.

2. Deep n-well sensor with pixel signal processing

The principle of operation of CMOS MAPS for charged particle detection is similar to the one proposed for visible light imaging. The device is built on a low resistivity p-type wafer with a thin ( about 10 µm) p-type epitaxial layer. The charge released by the incident particle moves by diffusion in the undepleted epitaxial layer. Electrons are then collected by the n-well/p-epi diode, within a typical time of a few tens of nanoseconds.

In conventional MAPS the voltage signal is read out via a source follower and then sent to peripheral electronics with sequential access, limiting their readout speed. Furthermore, in conventional MAPS charge-to-voltage conversion is provided by the collecting electrode capacitance, forcing the typical dimensions of the sensitive element to a few microns and reducing the signal collected by a single pixel.

To overcome these limitations of conventional

(3)

C 1

C 2 C F

V F

b 0 b 1 Gm

Vth b 1

b 0

C C

impedance node High A (s) RC−CR Shaper Preamplifier

I I

Latch Comparator

RST VDD

Fig. 2. Block diagram of the pixel level signal processing

MAPS we designed a new CMOS active pixel in a triple well deep submicron technology. The con- cept of our new sensor is illustrated in Fig. 1. In triple well commercial CMOS processes an n-well with a deep junction is available to ensure better insulation of the analog n-channel devices from the substrate and the neighboring digital devices.

In our design the deep n-well is used as a charge collecting electrode and also contains part of the front-end stage. This was possible since part of the n-channel devices of the analog readout electronics are located in the p-type well, physically over- lapped with the area of the sensitive element. In this way the collecting electrode can cover a large fraction of the elementary cell, maximizing the fill factor, and at the same time more room is available to develop more complex readout electronics at the pixel level.

The signal processing chain implemented includes a charge preamplifier, a shaper, a discriminator and some elementary logic functionality.

With the use of a charge preamplifier as a front-end element the charge sensitivity is independent of the capacitance of the charge collecting electrode, whose area can thus be extended. With the large sensing electrode area (about 1000 µm²), made possible with this new approach, charge collection with single pixel is very efficient, as shown in the following sections. Furthermore a large sensing electrode allows to increase the pixel pitch, without degrading collection efficiency, in applications were requirements on resolution are less stringent.

In the pixel design the area of the standard n- wells, which contains the p-channel devices for the analog and the digital part, has to be minimized.

These standard n-wells could in fact capture some fraction of the charge to the deep n-well collecting electrode, thereby degrading charge collection efficiency. So, in all the test structures implemented in the first prototype chip, the ratio of the deep n- well collecting electrode area to the area covered by all the n-wells is greater than 0.85.

2.1. Pixel level processor

The design of the readout electronics was car- ried out trying to minimize the area of the signal processor, the area of the standard n-wells and the power consumption, still taking into account the noise constraints. The block diagram of the pixel level processor is shown in Fig. 2 and is described in detail in [6].

The first stage of the signal processing is a high sensitivity charge preamplifier with continuous charge reset. The input device of the preamplifier was optimized for a pixel capacitance of 100 fF. Unfortunately the actual sensor capacitance, measured on test structures, resulted much higher than the value assumed during design and simulation phases and the noise performances of the first prototype chips were therefore affected. A more realistic sensor capacitance has been con- sidered in the design of the new chips (already in production) with an expected improvement of the

(4)

signal-to-noise ratio of about a factor of three.

The preamplifier is followed by an RC-CR shaper with a programmable peaking time (500 ns, 1 µs, 2 µs). The relatively long peaking times were chosen to avoid ballistic deficit in the case of collection time of 100 ns or larger. Preliminary physical device simulation, presented in the next section, indicates shorter collection time making room for a possible reduction of the peaking time in future versions of the processing chain.

To provide binary information at the pixel level the signal at the shaper output is sent to a discriminator, and compared to an externally preset threshold voltage. A NOR latch is then used to store the data until a reset is sent to restore the initial conditions.

3. Physical Device Simulation

In order to study the charge collection mechanism of the sensor and its time properties we performed a detailed physical simulation of the pixel cell with the ISE-TCAD package [7]. Preliminary results presented here were obtained with a 2-D simulation while a more accurate 3-D representa- tion of the pixel geometry is presently under way.

-20 -10 0 10 20

-15 -10 -5 0 5 10 15 20

DopingConcentration 2.0E+20 7.2E+16 2.6E+13 -2.6E+13 -7.2E+16 -2.0E+20 p− epitaxial layer

MIP Deep N−well

p+ substrate

N−well

Fig. 3. Elementary cell used in the physical device simulation. Dimensions are in µm.

The simulated structure is composed of three pixel cells identical to the one shown in Fig. 3.

Since thermal diffusion is the main transport mechanism in CMOS MAPS (the epitaxial layer is not depleted due to its relatively high doping concen- tration) parameters like minority carrier lifetime

Fig. 4. Charge collected by pixels (central and adjacent ones) as a function of the impact point distance from the center of the central pixel. Epitaxial layer thickness is 15 µm.

and mobility are crucial to understand the charge collection mechanism. All those sensitive parameters were chosen following appropriate dependen- cies and physical models [7]. Non-reflective boundary conditions were applied at the boundary of the simulated structure, artificially reducing the minority carrier lifetime, in those regions, to exclude from the collection process electrons diffusing close to detector boundaries. In fact standard reflective boundary conditions would lead to overstimate the signal by collecting charge which would normally be lost, since it diffuses far away from the impact point.

The implemented doping profiles for the mod- elled structures is a simplified version of a standard triple well process technology. The active volume of the detector is the epitaxial layer, since most of the collected charge originates in it. Information on the epitaxial layer thickness was not available from the foundry, so we studied the response of the simulation as a function of this parameter. The low resistivity substrate contributes to the collected charge only for a few microns, due to the very short minority carrier lifetime in this region (about 10 ns).

In the simulated structure the substrate thickness was set to 20 µm.

The heavy-ion model, available for transient sim- ulations, was used to describe the excess of charge due to the passage of an ionizing particle. A uni- form charge distribution along the track with a

(5)

value of 80 e-h/µm (most probable value for MIPs) was assumed. We studied the charge collection efficiency and the collection time varying the impact point of the incident particle across the cell shown in Fig. 3. As expected, the collected charge increases with the epitaxial layer thickness. Due to the relatively short minority carrier lifetime in this region (about 10 µs), the collected signal by single pixel saturates for an epitaxial layer thickness of about 15 µm. The charge collected by the central pixel and the adjacent ones is shown in Fig. 4 for an epitaxial layer of 15 µm. Due to the large sensing electrode area (between 50% and 80% of the pixel area, for the designed structures), charge collection is very efficient, resulting in a maximum single pixel signal of about 1300 e-. In conventional MAPS, single pixel signal is lower by about a factor of two for the same epitaxial layer thickness [2].

Simulation also indicates a relatively fast collection time: for a 15 µm thick epitaxial layer the central pixel collects 90% of the signal in about 20-40 ns, depending on the particle impact point position inside the cell.

4. Experimental Results

Preliminary results shown in this section were obtained with the first prototype of the sensor described in the previous sections.

4.1. Test structure description

The prototype chip includes six pixel elementary cells, with different collecting electrode area and available testing modality. In all six pixels the shaper and the latch output signals can be measured with an active probe devices (about 20 fF input capacitance).

The six pixels, referred in the following as channel 1 to 6, have the same readout chain described in section 2.1. Channels 1, 2 and 5 have been designed to study the front-end electronics performance through external charge injection, via an integrated injection capacitance (30 fF MIM capacitor in series with the input device gate of the preamplifier). In channel 2, which is not connected

Pixel Injection Collecting Channel Capacitance Electrode

1 YES NO

2 YES NO / 100 fF simulating detector capacitance

3 NO 1730 µm²

4 NO 2670 µm²

5 YES 830 µm²

6 NO 830 µm²

Table 1

Characteristics of the six single pixel channels.

to the deep n-well sensor, we integrated a 100 fF MIM capacitor, shunting the preamplifier input gate, to simulate the detector capacitance. Chan- nels 3, 4, 5, 6, have the preamplifier input device gate connected to deep n-well sensor and can be tested with infrared radiation or particle sources.

The characteristics of the six channels are summa- rized in Table 1.

4.2. Front-end Characterization

The front-end channel performance was measured in channels equipped with calibration injection capacitance (1, 2, 5) . The signal at the shaper output and the corresponding latch response is shown in Fig. 5 for a charge pulse of about 800 electrons. When the shaper signal level crosses the discriminator threshold, the latch flips its state and mantains the information until a reset is sent to restore the initial level.

In Fig. 6 the peak value of the shaper response is shown as a function of the injected charge (channel 5). A gain of about 450 mV/fC was obtained for this channel interpolating the data points with a linear fit. Results obtained from post layout simulation (PLS) are in good agreement, within 10%, with the measured gains for all the tested channels.

The equivalent noise charge (ENC) was measured in the channels with calibration capacitance and it is shown in Fig. 7 as a function of the total channel capacitance. There are several contributions to the total capacitance (CT) shunting the charge sensitive amplifier input.

They are, in increasing order, the feedback ca-

(6)

Channel 2

0.5 5 . 1

5

−0.

0.08 0

Shaperoutput[V]

tP= 1µµµµs

−0.5 0 0.5 1 1.5

0 5 10 15

Reset[V]

t [µµµµs]

Latchoutput[V]

0.02

− 0.02

0.06 0.04

−

0 1

Fig. 5. Signal at the shaper and at the latch output. The reset signal restore initial conditions.

0 20 40 60 80 100 120

0 200 400 600 800 1000 1200

Measurements PLS

V peak [mV]

Qin [e-]

448 mV/fC

430 mV/fC

Channel 5 tp=1 µs

Fig. 6. Signal at the shaper output as a function of the injected charge. Measurement data and post layout simulation are shown for channel 5.

pacitance (Cf =8 fF), the preamplifier input capacitance (Cin=14 fF), the injection capacitance (Cinj =30 fF) and the detector capacitance CD, which scales with the sensor area. This last con- tribution is the dominant one and accounts for about 270 fF for channel 5, the pixel with the smallest sensor area (830 µm²). As expected from

0 50 100 150 200 250

0 50 100 150 200 250 300 350

ENC [e- rms]

CT [fF]

ENC = 11e^- + 425e^-/pF

tp=1 µs

Fig. 7. Equivalent noise charge as a function of the total channel capacitance shunting the charge pramplifier input (channel 1, 2, 5 from left to right).

the model [6], noise increases linearly with the total channel capacitance:

EN C = 11e⁻+ 425e⁻/pF (1)

resulting in an equivalent noise charge of about 150 e⁻ for channel 5.

The effects of digital switching noise on the performance of the readout electronics were also in- vestigated. For this purpose a cascade of four in- verters was integrated close to channel 3. No sig- nificant change was observed in the noise performances of any of the channels when the inverter chain was operated at frequencies up to 1 MHz.

4.3. Device Calibration with Soft X-ray

The response of the sensor was tested with radiation sources. Soft X-ray from an⁵⁵Fe source were used to measure the conversion gain and the equivalent noise charge in channels not equipped with calibration capacitance. Photons that interacts in the silicon, via the photoelectric effect, would release all their energy in the detector. For the 5.9 keV line this corresponds to 1640 e/h pairs gener- ated in the silicon. When the X-ray converts close to collecting electrode, nearby the small depletion region below the electrode, one can assume a 100%

collection efficiency. Those events would generate a peak in the single pixel signal amplitude, whose position can be used to calibrate the pixel gain.

In case the photon interaction is in the active volume, but far away from the collecting electrode, the

(7)

Fig. 8. Signal pulse height distribution (single pixel) for photons emitted from an⁵⁵F e source. Noise events, with the correct normalization factor, are superimposed (dark histogram).

charge realeased would be only partially collected by a single pixel. In this case charge moves by thermal diffusion and is naturally spread among several pixels. For those events the single pixel would collect a lower signal.

In Fig. 8 we show the response of the sensor to the⁵⁵Fe X-ray source. There is a clear peak in the signal pulse height distribution at 105 mV, which corresponds to photon interactions with 100%

charge collection efficiency. At lower pulse height there is a clear excess of signal events with respect to the noise event level. Those events corresponds to photon interaction with charge only partially collected. The region of the spectrum below 70 mV was cut by the threshold of the digital scope used for the acquisition.

Using the ⁵⁵Fe calibration data, a gain of 400 mV/fC and an equivalent noise charge of about 125 e⁻ were measured for channel 6. Both results are in good agreement with the post layout simulation and with measurements performed, with the calibration capacitance, on channel 5, which has same sensor area as channel 6 (Table 1).

4.4. Response to electrons from a⁹⁰Sr/⁹⁰Y beta source

Response of the sensor to charged particles was studied using a ⁹⁰Sr/⁹⁰Y beta source. Electrons from this source, coming from two different beta decays, have a wide energy spectrum with end

Fig. 9. Signal pulse height distribution (single pixel) for electrons emitted from a ⁹⁰Sr/⁹⁰Y beta source. Noise events, with the correct normalization factor, are superimposed (dark histogram).

point at about 2.5 MeV. Results presented here were obtained with a simple setup. The sensor under test was positioned between the beta source and a scintillator. The acquisition system was trig- gered by the coincidence between the scintillator and the digital output of the pixel, indicating that the sensor was fired. In this preliminary test no selection on particle energy was applied. Anyway, given the energy spectrum of the electrons cross- ing the detector, about 50% of the signal events recorded were due to minimum ionizing particles (MIP), giving rise to a characteristic Landau peak in the signal amplitude. For the remaining signal events, due to lower energy electrons, the charge released in the sensor is higher than for a MIP, so those events deformate the Landau shape or can even saturate the shaper output.

Results of this test are shown in Fig. 9, where a clear Landau peak is visible with a most probable signal at about 80 mV. Using the⁵⁵Fe calibration data, the signal from those MIPs corresponds to about 1250 electrons collected by a single pixel, in agreement with the device simulation expectations shown in section 3. As expected towards the end of the spectrum the Landau shape is deformated by events with higher charge deposition.

Considering the single pixel noise measured for this channel (8 mV), and the response to the MIPs from the beta source, we measure a most probable signal-to-noise ratio of about 10.

(8)

5. Conclusions and perspectives

In this paper we presented a new CMOS active pixel which exploits the triple well technology to implement, at the pixel level, a more complex signal processor and to increase the size of the charge collecting electrode with respect to conventional MAPS. This was possible using the deep n-well, available in triple well technology, as sensing electrode and placing, in the same physical area, part of the readout electronics.

The first prototype chips were successfully tested. Measurements presented in this work are very encouraging and demonstrate the full functionality of the device: sensor and readout electronics. A good agreement has been observed amongs the various results presented and the device simulation.

The signal-to-noise ratio, about 10 for the present device, will be improved by a factor of three in the next chip version, with a better op- timization of the front-end electronics. The new chip will also include a pixel matrix with a simple sequential readout.

The idea explored with this work has several potential advantages with respect to conventional MAPS.

– The implemented readout scheme of the new MAPS is based on the standard processing chain for capacitive detector (i.e. charge preamplifier, shaper, discriminator) and it is thus compatible with architectures performing sparsified readout at the elementary cell level. This feature, that we plan to implement in our device, will address the readout speed limitation of conventional MAPS.

– Large sensing electrode area (about 1000 µm²), obtainable with this approach, allows very efficient charge collection within single pixel.

– The possibility to extend the size of the collecting electrode allows to increase the pixel pitch, without degrading collection efficiency, in applications where requirements on resolution are less stringent.

Radiation resistance of the new MAPS device are currently under study. In the chosen 0.13 µm technology, thanks to the thin gate oxide (about 2 nm), CMOS devices have shown a very high degree

of radiation tolerance, allowing the design of open structure devices with a modest degradation of the radiation hardness [8]. Furthermore with the proposed front-end readout, based on a charge preamplifier with continuous reset, the noise is expected to be less sensitive to diode leakage current induced by radiation damage. Charge trapping from bulk damage is then expected to be the dominant effect on sensor performace deterioration, reducing the signal collected in irradiated devices. Anyway this effect is probably less important than in standard MAPS, thanks to the relatively high single pixel signal, related to the extended size of the collecting electrode with respect to the pixel area.

The future developments of this new CMOS MAPS device will be pursued within the new SLIM collaboration (Silicon detectors with Low Interaction with Material), supported by the Isti- tuto Nazionale di Fisica Nucleare and the Italian Ministry for Education, University and Research.

The final goal of this R&D project is to develop a MAPS matrix with sparsified readout at the pixel level, suitable to be used in a trigger system based on associative memories.

References

[1] E. R. Fossum, IEEE Trans. El. Dev. 44 (1997) 1689.

[2] G. Deptuch et al., IEEE Trans. Nucl. Sci. 49 (2002) 601.

[3] H. S. Matis et al., IEEE Trans. Nucl. Sci. 50 (2004) 1020.

[4] D. Passeri et al., Nucl. Instrum. Methods, A518 (2004) 482.

[5] G. Verner et al., Nucl. Instrum. Methods, A541 (2005) 166.

[6] L. Ratti et al., Contributed paper to Proceedings of 10^th European Symposium on Semiconductor Detectors, Wildbad Kreuth, Germany, June 12-16 2005, to be published in Nucl. Instrum. Methods, A.

[7] Software Release 9.0 User’s Manual, ISE TCAD, ISE Integrated System Engineering AG, Zurich, CH, Switzerland.

[8] V. Re et al. Contributed paper to 2005 IEEE Nuclear and Space Radiation Effects Conference, Radiation Effects Data Workshop, Seattle, WA, USA, July 11-15 2005.