Appendice B. Il codice C++

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Appendice B. Il codice C++

/************************************************************************ ******* * FILENAME * emul_driv.c * * DESCRIPTION

* dsp software for spada emulator *

**********************************************************************/ #include <stdio.h>

#include "orstypes.h" #include <c6x.h>

#include "c6713CPT.h" /* onboard register */ #include "sys6713.h" /* onboard functions */ #include "Debug.h"

#include "drv_1624.h" /* driver for onboard thermometer/EEPROM */ #include "fpga.h" /* fpga load */

#include "emul_reg.h" /* emulator register definitions*/

#include "c6713CPT_def_fpga.h" /* fpga register */

#include "flash29lv640.h" /* pogramm flash with routine MyProg */ #include "c6x.h"

#include "int.h" //interrupt handlers

#include "c6713_dma.h" //dma register and functions definitions

#include "spada_system.h" //general purpose spada system declarations

/******************************************************************** * Function prototypes *********************************************************************/ void c_int00(void); /********************************************************************/ int iGblError; /********************************************************************/ /********************************************************************/ #define OK 0 #define ERROR 1 /*********************************************************************/ // boot //

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//

//*********************************************************************/ #pragma CODE_SECTION (boot, "boot"); /*

#pragma FUNC_NEVER_RETURNS (boot); //

__asm(" .global _c_int00");

void boot(void) {

//register keyword asks the compiler to store the variable in a machine's register

register INT16U* pFlash = (INT16U*)(C6713CPT_FLASH_BASE +

0x400);//0x80);//#define C6713CPT_FLASH_BASE 0x90000000 /* onboard flash memory */

register INT16U* pRAM = (INT16U*)0x400;//0x80;//perché???

register INT32U i; // types defined in orstypes.h

__asm(" NOP 5 ");

__asm(" B.S1 _c_int00 "); // jump to c_int00 __asm(" NOP 5 ");

}

/**********************************************************************/ void Delay(int Value)

{ int volatile n; for (n = 1; n <= Value; n++) {} } int GblData = 0xFFFFFFFF; /********************************************************************* * FUNCTION : main * *********************************************************************/ /*global variable*/

volatile INT32U DEBUG_CFG_REG; volatile INT32U DEBUG_VAL; INT32U* pDEBUG_VAL;

volatile INT32U CFG_REG_VALUE;

volatile INT32U DEBUG_VAL; char acCmd[BUFF_SIZE]; int read_index;

int data_count = 0;

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int i = 0; INT32U j= 0;

char* cpBuffWr;//rx buffer read pointer char* cpBuffRd;//tx buffer write pointer int main() { INT32U temp_value; INT32U uiCfgWord; /***********************************************************************/ // DSP initialization cpBuffWr = acCmd; cpBuffRd = acCmd; i = 0;

C6xCptInit(&sC6xCptInitRegs);//DSP register init

DebugInit(); //115200, TxIntDisabled , RxIntEnabled, FlowControlDisabled

/* load fpga */

if (FpgaLoad( (INT32U*)0x80000000, 2041296) != FPGA_OK) {

int a = FpgaLoad( (INT32U*)0x80000000, 2041296); C6713CPT_LED_RED_ON; while(1); } else { DebugOutConstString("fpga loaded"); DebugOutConstString("/r/n"); DebugFlush; EMUL_GREEN_LED_ON; Delay(1000000); EMUL_GREEN_LED_OFF; Delay(1000000); EMUL_GREEN_LED_ON; Delay(1000000); EMUL_GREEN_LED_OFF; Delay(1000000); EMUL_GREEN_LED_OFF; Delay(1000000); EMUL_GREEN_LED_ON; Delay(1000000); EMUL_GREEN_LED_OFF; Delay(1000000); EMUL_GREEN_LED_ON; Delay(1000000); EMUL_GREEN_LED_OFF; } /*interrupt setup*/

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C6xIntEnable(C6X_INT7);//uart

C6713CPT_EINT7_EN = 0x80; //enable only uart interrupt C6xGlobalIntEnable(); EMUL_RED_LED_OFF; EMUL_GREEN_LED_OFF; C6713CPT_LED_RED_OFF; C6713CPT_LED_GREEN_OFF; while(1) {

while (j<32) //30 dwords, one for each counter plus 2 global configuration dword

//for CFG_REG_SEL and CFG_REG_EN { while(data_count > 0) { temp_array[i] = *cpBuffRd; i++; data_count--;

if(++cpBuffRd == acCmd+ BUFF_SIZE)

cpBuffRd = acCmd;

if( i == 4 ) //a new dword has been received by the UART and is ready to be used

{

i = 0;

uiCfgWord = (unsigned char)temp_array[0]; uiCfgWord = uiCfgWord << 8;

uiCfgWord |= (unsigned char) temp_array[1]; uiCfgWord = uiCfgWord << 8;

uiCfgWord |= (unsigned char) temp_array[2]; uiCfgWord = uiCfgWord << 8;

uiCfgWord |= (unsigned char) temp_array[3];

if (j<31)

{

*( (volatile INT32U *) (0xA0200004 + j*4) ) = uiCfgWord; //*( (volatile INT32U *) (0xA0200000)) = uiCfgWord; EMUL_VALIDATE_DATA;

//pDEBUG_VAL = ( (INT32U *) (0xA0200004 + j*4) ); //DEBUG_VAL = *pDEBUG_VAL;

*( (volatile INT32U *) (0xA0200000) ) |= 0x00000001;

EMUL_VALIDATE_DATA;

Delay(100000);

*( (volatile INT32U *) (0xA0200000) ) &= 0x00000000;

EMUL_VALIDATE_DATA;

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*( (volatile INT32U *) (0xA0200000) ) |= 0x00000002;

EMUL_VALIDATE_DATA;

Delay(100000);

*( (volatile INT32U *) (0xA0200000) ) &= 0x00000000;

EMUL_VALIDATE_DATA; j++; } else {

*( (volatile INT32U *) (0xA0200004 + (j-1)*4) ) = uiCfgWord; EMUL_VALIDATE_DATA;

//pDEBUG_VAL = ( (INT32U *) (0xA0200004 + (j-1)*4) ); //DEBUG_VAL = *pDEBUG_VAL;

//EMUL_GREEN_LED_TOGGLE;

//pDEBUG_VAL = ( (INT32U *) (0xA0200000) ); //DEBUG_CFG_REG = *pDEBUG_VAL;

//DEBUG_VAL = *pDEBUG_VAL;

j++;

}

//DebugOutConstString("new value written"); //DebugOutConstString("/r/n"); //DebugFlush; }//end if } }//end while // EMUL_RED_LED_TOGGLE; // Delay(1000000); //DebugOutConstString; //DebugOutConstString("/r/n"); //DebugFlush;

//end of uart transfer j = 0; // C6713CPT_LED_GREEN_TOGGLE // Delay(100000); } }//end of main

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/***********************************************************************/ // MyProg

//

// programmiert das Flash im Sector 0 (64kByte) //

// Set Programmcounter to MyProg and Go

/***********************************************************************/ void MyProg(void)

{

int volatile RetCode;

RetCode = FlashEraseSector (0x00000);

if (RetCode)

exit();

RetCode = FlashProgramming ((INT16U*)0x0000, //INT16U* pSrc,

0x00000000L, //INT32U FlashAddress, 0x8000); //int Numwords) if (RetCode) exit();

C6713CPT_MCR &= ~0x40; /* Turn off user LED */

/* Turn off user LED in FPGA register */ /* C6713CPT_FPGA_LED address = 0xB0080001 */ C6713CPT_FPGA_LED = 0; while(1); } /***********************************************************************/ /*************************************************** * * * file : INT.C * * * **************************************************** * description: Implementation of Interrupt Handler * ****************************************************/ #include "emul_reg.h" #include "orstypes.h" #include "c6713_dma.h" #include "debug.h" #include "debug_hw.h" #include "spada_system.h"

interrupt void UartDataReadyISR_7() {

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extern char* cpBuffWr;//rx buffer read pointer extern char* cpBuffRd;//tx buffer write pointer extern char acCmd[BUFF_SIZE];

extern int data_count;

if (data_count < BUFF_SIZE) //free space condition {*cpBuffWr = DEBUG_RECEIVE();

data_count ++;

if(++cpBuffWr == acCmd + BUFF_SIZE) cpBuffWr = acCmd; }// end of if }//end of routine /************************************************************************ ****** * * file : EMUL_REG.H

* project : Spada Emulator * * ************************************************************************* ****** * ************************************************************************* *****/ #ifndef _EMUL_REG_H_ #define _EMUL_REG_H_ #include "c6713cpt.h" #include "orstypes.h"

/*EMUL base address*/

#define EMUL_BASE_ADDR 0x00200000

#define EMUL_CFG_REG_ADDR (C6211_CE2_BASE+ EMUL_BASE_ADDR +0x000000) #define EMUL_VALID_REG_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR + 0x0000F4)

#define EMUL_FRAME_INFO_REG_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR)

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#define EMUL_SPADA_CFG_2_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR + 0x00008) #define EMUL_SPADA_CFG_3_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR + 0x0000C) #define EMUL_SPADA_CFG_4_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR + 0x00010) #define EMUL_SPADA_CFG_5_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR + 0x00014) #define EMUL_SPADA_CFG_6_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR + 0x00018) #define EMUL_SPADA_CFG_7_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR + 0x0001C) #define EMUL_SPADA_CFG_8_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR + 0x00020) #define EMUL_SPADA_CFG_9_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR + 0x00024) #define EMUL_SPADA_CFG_10_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00028) #define EMUL_SPADA_CFG_11_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x0002C) #define EMUL_SPADA_CFG_12_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00030) #define EMUL_SPADA_CFG_13_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00034) #define EMUL_SPADA_CFG_14_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00038) #define EMUL_SPADA_CFG_15_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x0003C) #define EMUL_SPADA_CFG_16_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00040) #define EMUL_SPADA_CFG_17_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00044) #define EMUL_SPADA_CFG_18_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00048) #define EMUL_SPADA_CFG_19_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x0004C) #define EMUL_SPADA_CFG_20_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00050) #define EMUL_SPADA_CFG_21_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00054) #define EMUL_SPADA_CFG_22_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00058) #define EMUL_SPADA_CFG_23_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x0005C) #define EMUL_SPADA_CFG_24_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00060) #define EMUL_SPADA_CFG_25_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00064) #define EMUL_SPADA_CFG_26_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00068) #define EMUL_SPADA_CFG_27_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x0006C) #define EMUL_SPADA_CFG_28_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00070) #define EMUL_SPADA_CFG_29_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00074) #define EMUL_SPADA_CFG_30_ADDR (C6211_CE2_BASE+EMUL_BASE_ADDR + 0x00078)

#define EMUL_CFG_EN_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR + 0x0007C) #define EMUL_CFG_SEL_ADDR (C6211_CE2_BASE + EMUL_BASE_ADDR + 0x00080)

/* EMUL registers definitions*/

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#define EMUL_CFG_REG EMUL_REG(EMUL_CFG_REG_ADDR)

#define EMUL_VALID_REG EMUL_REG(EMUL_VALID_REG_ADDR)

#define EMUL_SPADA_CFG_1_REG EMUL_REG(EMUL_SPADA_CFG_1_ADDR) #define EMUL_SPADA_CFG_2_REG EMUL_REG(EMUL_SPADA_CFG_2_ADDR) #define EMUL_SPADA_CFG_3_REG EMUL_REG(EMUL_SPADA_CFG_3_ADDR) #define EMUL_SPADA_CFG_4_REG EMUL_REG(EMUL_SPADA_CFG_4_ADDR) #define EMUL_SPADA_CFG_5_REG EMUL_REG(EMUL_SPADA_CFG_5_ADDR) #define EMUL_SPADA_CFG_6_REG EMUL_REG(EMUL_SPADA_CFG_6_ADDR) #define EMUL_SPADA_CFG_7_REG EMUL_REG(EMUL_SPADA_CFG_7_ADDR) #define EMUL_SPADA_CFG_8_REG EMUL_REG(EMUL_SPADA_CFG_8_ADDR) #define EMUL_SPADA_CFG_9_REG EMUL_REG(EMUL_SPADA_CFG_9_ADDR) #define EMUL_SPADA_CFG_10_REG EMUL_REG(EMUL_SPADA_CFG_10_ADDR) #define EMUL_SPADA_CFG_11_REG EMUL_REG(EMUL_SPADA_CFG_11_ADDR) #define EMUL_SPADA_CFG_12_REG EMUL_REG(EMUL_SPADA_CFG_12_ADDR) #define EMUL_SPADA_CFG_13_REG EMUL_REG(EMUL_SPADA_CFG_13_ADDR) #define EMUL_SPADA_CFG_14_REG EMUL_REG(EMUL_SPADA_CFG_14_ADDR) #define EMUL_SPADA_CFG_15_REG EMUL_REG(EMUL_SPADA_CFG_15_ADDR) #define EMUL_SPADA_CFG_16_REG EMUL_REG(EMUL_SPADA_CFG_16_ADDR) #define EMUL_SPADA_CFG_17_REG EMUL_REG(EMUL_SPADA_CFG_17_ADDR) #define EMUL_SPADA_CFG_18_REG EMUL_REG(EMUL_SPADA_CFG_18_ADDR) #define EMUL_SPADA_CFG_19_REG EMUL_REG(EMUL_SPADA_CFG_19_ADDR) #define EMUL_SPADA_CFG_20_REG EMUL_REG(EMUL_SPADA_CFG_20_ADDR) #define EMUL_SPADA_CFG_21_REG EMUL_REG(EMUL_SPADA_CFG_21_ADDR) #define EMUL_SPADA_CFG_22_REG EMUL_REG(EMUL_SPADA_CFG_22_ADDR) #define EMUL_SPADA_CFG_23_REG EMUL_REG(EMUL_SPADA_CFG_23_ADDR) #define EMUL_SPADA_CFG_24_REG EMUL_REG(EMUL_SPADA_CFG_24_ADDR) #define EMUL_SPADA_CFG_25_REG EMUL_REG(EMUL_SPADA_CFG_25_ADDR) #define EMUL_SPADA_CFG_26_REG EMUL_REG(EMUL_SPADA_CFG_26_ADDR) #define EMUL_SPADA_CFG_27_REG EMUL_REG(EMUL_SPADA_CFG_27_ADDR) #define EMUL_SPADA_CFG_28_REG EMUL_REG(EMUL_SPADA_CFG_28_ADDR) #define EMUL_SPADA_CFG_29_REG EMUL_REG(EMUL_SPADA_CFG_29_ADDR) #define EMUL_SPADA_CFG_30_REG EMUL_REG(EMUL_SPADA_CFG_30_ADDR)

#define EMUL_CFG_EN_REG EMUL_REG(EMUL_CFG_EN_ADDR)

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#define EMUL_FRAME_INFO_REG EMUL_REG(EMUL_FRAME_INFO_REG_ADDR)

/*EMUL leds control*/

#define EMUL_RED_LED_ON {EMUL_CFG_REG |= 0x00000002;} #define EMUL_RED_LED_OFF {EMUL_CFG_REG &= ~0x00000002;} #define EMUL_RED_LED_TOGGLE {EMUL_CFG_REG ^= 0x00000002;}

#define EMUL_GREEN_LED_ON {EMUL_CFG_REG |= 0x00000001;} #define EMUL_GREEN_LED_OFF {EMUL_CFG_REG &= ~0x00000001;} #define EMUL_GREEN_LED_TOGGLE {EMUL_CFG_REG ^= 0x00000001;}

/*EMUL validation register control*/

#define EMUL_VALIDATE_DATA {EMUL_VALID_REG |= 0x00000001;}

/*EMUL period setting*/

#define EMUL_SET_PERIOD(period) {EMUL_CFG_REG |= period;} //period is 10us multilple

#define BUFF_SIZE 128